Cadence Design Systems has announced that NSITEXE deployed the Cadence digital design full flow to accelerate the delivery of its high-efficiency, high-quality data flow processor (DFP) IP for automotive and industrial applications. Using the integrated Cadence digital full flow, starting with the Genus Synthesis Solution, NSITEXE successfully reduced turnaround time by 75% while also improving power by 8.5%, performance by 35% and reducing area by 3.5% when compared with its previous competitive solution.
The Cadence flow deployed at NSITEXE included the Genus Synthesis Solution, Joules RTL Power Solution, Conformal Equivalence Checker, Modus DFT Software Solution and Innovus Implementation System. The tightly integrated flow provided NSITEXE with a common Cadence database and user interface (UI), eliminating the need for data transfer between tools and communication exchanges between multiple engineers.
The Genus Synthesis Solution played a critical role in the flow, enabling NSITEXE to accelerate iterations from register-transfer level (RTL) to layout. Additionally, the shared engines between the Genus Synthesis Solution and the Innovus Implementation System helped NSITEXE avoid unnecessary iterations and identify design bottlenecks.
“To accelerate the delivery of our high-efficiency, high-quality DFP IP, we needed a solution that enabled us to achieve our aggressive turnaround time goals,” said Hideki Sugimoto, CTO of NSITEXE. “After an extensive evaluation, we decided to implement the Cadence full flow because it offered a tightly integrated design environment that created efficiencies for our team and produced optimal PPA results. We plan to use the Cadence flow to advance our next-generation IP for the rapidly evolving automotive and industrial markets.”
The Cadence digital design full flow is part of the company’s broader digital and signoff suite, which provides customers with an integrated full flow, delivering better predictability and a faster path to design closure. It supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence.
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