Asynchronous (dual-clock) FIFOs are important functions in high-speed digital design, especially when data needs to be transferred between two clock domains. Let’s talk about the implementation of such a FIFO, and the nuances of some of the details.
One of the central elements in the design is the “true dual port” RAM block. Describe the essential features of this block.
In order to implement a FIFO, a write address counter and a read address counter are required. Each counter wraps back to zero when it reaches its maximum count.
In order to determine the number of words currently in the FIFO, the values of the two counters must be subtracted. However, the two counters are in two different clock domains, which means that the value of each one needs to be transferred to the other clock domain. Why is Gray code used for this purpose?
Given that it takes a significant number of clocks to transfer a counter value from one clock domain to the other, what does this imply about the overall data latency through the FIFO?
What about the input side of the FIFO? Does the synchronization delay create any danger that it will overwrite old data before it can be read?
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