CC Blog  Question 1: What is the probably of a flip-flop with a uniformly-distributed asynchronous input going metastable?

Answer 1: The probably that a flip-flop with a uniformly-distributed asynchronous input will go metastable is a function of how wide its “window of opportunity” (the sum of the setup and hold times) is and the clock period. It is proportional to (and less than, because of manufacturer’s testing margins) the ratio of these two times.

Question 2: How long does it take for a flip-flop in a metastable state to resolve itself?

Answer 2: There is no definite time for a flip-flop to resolve a metastable state. All we can say is that there is some probability that it will remain metastable after a given amount of time has passed. This is usually a rapidly-decaying exponential funciton. The scale factor, or time constant associated with this function is determined by factors such as the internal gain of the flip-flop and the speed of the active devices used in its implementation.

Question 3: Why does putting multiple flip-flops in series reduce the probability of having a metastable output at the output?

Answer 3: When two flip-flops are placed in series, the probability of the second one going metastable is the product of two factors: the probabiliy of the first one going metastable in the first place, and the probability of that metastable state lasting exactly as long as the clock period. Both of these factors are much less than unity, so their product is even lower still.

A third flip-flop is sometimes used, which reduces the chances of metastability to infinitesimal levels.

Question 4: Under what conditions will a metastable condition propagate from one flip-flop to the next?

Answer 4: In order for the second flip-flop in a chain to go metastable, it’s input must be changing in the “window of opportunity” defined by its setup and hold times.

Note that if the first flip-flop has not yet resolved itself by the time the next clock edge comes along, the second one will not generally go metastable. This is because the circuitry of the flip-flop is always designed so that the input threshold voltage differs enough from the metastable output voltage by enough of a margin to guarantee that the second flip-flop will interpret it as a definite high or definite low.

Therefore, the only way that the second flip-flop can go metastable is if the first one’s metastable state had just started to resolve itself at the next clock edge, such that its output was passing through the second one’s input threshold at that moment.

Contributor: David Tweed

Don't miss out on upcoming issues of Circuit Cellar. Subscribe today!

Note: We’ve made the October 2017 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

Would you like to write for Circuit Cellar? We are always accepting articles/posts from the technical community. Get in touch with us and let's discuss your ideas.