Issue 296: EQ Answers

Answer 1—The frequency generated at the QB output of the counter is 16.000 MHz × 3 / 13 = 3.6923 MHz. The ratio between this and 3.6864 MHz is 1.0016, so the error expressed as a percentage is +0.16%. This is well within the tolerance required for asynchronous serial communications.

Answer 2—The circuit generates rising edges (also falling edges) at intervals of 4 clocks, 4 clocks and 5 clocks, but the ideal spacing would be 4.3333 clocks. Therefore two of the intervals are short by 1/3 clock and one of them is long by 2/3 clock.

Therefore, the cycle-to-cycle peak-to-peak jitter is 1/3 + 2/3 = 1 full input clock period, or 62.5 ns. But taking an average over a complete group of 13 clocks, no edge is displaced from its “ideal” location by more than 1/3 clock, or 20.8 ns.

Answer 3—The following table shows the divider ratios required for various standard baud rates.297 eq answers

As you can see, a modern UART can generate the clocks for baud rates up to 38400 with the exact same error as the 3/13 counter scheme — note that 26 and 52 are multiples of 13. But above that, the frequency error increases. This is why microcontrollers with built-in UARTs often run at “oddball” frequencies such as 11.0592 MHz or 12.288 MHz — these freqeuncies can be easily divided down to produce precisely correct baud rates.

Answer 4—A UART receiver waits for the leading edge of the start bit, and then samples the next 10 bits in the center of each bit “cell”. If by the time it gets to the 10th cell, the sampling point at the receiver has moved beyond the edge of the 10th bit (the stop bit) defined by the transmitter, the transmission will fail. This means that the timing error must be no more than ± 1/2 bit over a 9.5-bit span, or a total error between transmitter and receiver of ±5.26%. If the error is split evenly, this means that each baud rate generator must be accurate to within ±2.63%.

However, in reality, the receiver cannot determine the location of the leading edge precisely. Since it is using a 16× clock to do the sampling, there could be as much as 1/16 of a bit delay before the receiver actually recognizes the start bit, and all of its sampling points for the subsequent bits will be delayed by that amount. This means that the timing error must be no more than ± 7/16 of a bit by the time we get to the last bit, which means that the maximum total error is ±4.60%, or ±2.30% for each baud rate generator.



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Issue 296: EQ Answers

by Circuit Cellar Staff time to read: 2 min