CC Blog Test Your EQ (Engineering Quotient)

EQ #42

What are some of the problems associated with software interrupt priorities?

For one thing, the startup latency of all the ISRs is increased by the time spent in the “master” ISR. This can be a problem in time-critical systems.

This scheme allows interrupts to be nested, so the stack must be large enough to handle the worst-case nesting of ISRs, on top of the worst-case nesting of non-interrupt subroutine calls. Finally, it is very tricky to do this in anything other than assembly language. If you want to use a high-level language, you’ll need to be intimately familiar with the language’s run-time library and how it handles interrupts and reentrancy in general.


Keep up-to-date with our FREE Weekly Newsletter!



Don't miss out on upcoming issues of Circuit Cellar.

Note: We’ve made the May 2020 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.


Would you like to write for Circuit Cellar? We are always accepting articles/posts from the technical community. Get in touch with us and let's discuss your ideas.

— ADVERTISMENT—

Advertise Here

Supporting Companies

Slider

Upcoming Events

Copyright © 2021 KCK Media Corp.

EQ #42

by Circuit Cellar Staff time to read: <1 min