Cypress Semiconductor Corp. recently started sampling 4-Mb asynchronous SRAMs with Error-Correcting Code (ECC). The on-chip ECC feature of the new SRAMs enables them to provide the highest levels of data reliability, without the need for additional error correction chips—simplifying designs and reducing board space. The devices ensure data reliability in a wide variety of industrial, military, communication, data processing, medical, consumer, and automotive applications.
Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress’s new asynchronous SRAM family performs all error correction functions inline, without user intervention, delivering best-in-class Soft Error Rate (SER) performance of less than 0.1 FIT/Mb (one FIT is equivalent to one error per billion hours of device operation). The new devices are pin-compatible with current asynchronous fast and low-power SRAMs, enabling customers to boost system reliability while retaining board layout. The 4-Mb SRAMs also include an optional error indication signal that indicates the correction of single-bit errors.
The Cypress 4-Mb asynchronous SRAMs are available in three options—Fast, MoBL and Fast with PowerSnooze—an additional power-saving Deep Sleep mode that achieves 15 µA (max) deep-sleep current for the 4-Mb SRAM. Each of the options is offered in industry standard ×8 and ×16 configurations. The devices operate at multiple voltages (1.8, 3, and 5 V) over –40°C to 85°C (Industrial) and –40°C to +125°C (Automotive-E) temperature ranges.
The new SRAMs are currently sampling in industrial temperature grade, with production expected in July 2015. These devices will be available in RoHS-compliant 32-pin SOIC, 32-pin TSOP II, 36-pin SOJ, 44-pin SOJ, 44-pin TSOP II and 48-ball VFBGA packages.
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