More Smarts, Wider Scope
PCB design tools and methods continue to evolve as they race to keep pace with faster, highly integrated electronics. Automated, rules-based chip placement is getting more sophisticated and tools are addressing the broader picture of the PCB design process.
By Jeff Child
Diagnostic fter decades of evolving their PCB design tool software packages, the leading tool vendors have the basics of PCB design nailed down—auto-routing, complex layer support, schematic capture and so on. In recent years, these companies have continued to come up with new enhancements to their tool suites, addressing a myriad of issues related to not just the PCB design itself, but the whole process surrounding it.
With that in mind, even in the last sixth months, PCB tool vendors have added a whole host of new capabilities to their offerings. These include special reliability analysis capabilities, sophisticated design-for-test (DFT) tools, extended team collaboration support and more.
High-Speed Signal Validation
Exemplifying these trends, in February Mentor Graphics started shipping its HyperLynx solution that provides automated and intelligent channel extraction for serializer/deserializer (SerDes) interfaces. HyperLynx PCB simulation technology for high-performance designs provides an end-to-end fully automated SerDes channel validation solution. Today’s advanced electronics products require intelligent high-speed design tools to ensure that designs perform as intended. With signaling rates of
50 Gbps becoming commonplace, and protocols like Ethernet pushing 400 Gbps bandwidth, traditional methods are insufficient. This is crucial for industries that demand superior high-speed performance such as automotive, networking, data centers, telecom and IoT/cloud-based products.
SerDes applies to interfaces like PCI Express (PCIe) that are used anywhere high-bandwidth is required. The problem is today’s hardware engineers lack time to fully understand the detailed signal integrity requirements of these interface protocols and may have limited access to signal integrity (SI) and 3D EM experts for counsel. Mentor’s new HyperLynx release provides tool-embedded protocol-specific channel compliance. The company claims it’s the industry’s first fully automatic validation tool for PCB SerDes interfaces. This includes a 3D explorer feature for design and layout optimization of non-uniform structures like breakouts and vias.
Using the new HyperLynx release, hardware engineers can easily perform protocol-specific compliance checks. The tool provides embedded protocol expertise for PCIe Gen3/4, USB 3.1 and COM-based technology for Ethernet and Optical Implementers Forum (OIF). Engineers can easily perform equalization optimization (CTLE, FFE, DFE) based on protocol architecture and constraints. HyperLynx’s 3D Explorer feature provides channel structure design and pre-layout optimization. Template-based 3D structure synthesis can be used for differential pair, BGA breakouts, via configurations, series-blocking capacitors and more (Figure 1).
This isn’t the first Mentor Graphics time came out with PCB design tools that address a new dimension of PCB design. In March 2017, the company released its Xpedition vibration and acceleration simulation product for PCB systems reliability and failure prediction. The Xpedition product augments mechanical analysis and physical testing by introducing virtual accelerated lifecycle testing much earlier in the design process. The tool lets you simulate during the design process to determine PCB reliability and reduce field failure rates. You can also detect components on the threshold of failure that would be missed during physical testing. Finally, you can analyze pin-level Von-Mises stress and deformation to determine failure probability and safety factors.
DFT Plugin Added
In its most recent enhancement to its PCB tools offering, in February Zuken announced that it teamed up with boundary scan tool vendor XJTAG to add a plugin that enhances Zuken’s CR-8000 PCB Design Suite with a design for test (DFT) capability. . …
Read the full article in the June 335 issue of Circuit Cellar
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