Problem 1: You have decided to build a small computer from discrete transistors as a demonstration. After researching the available technologies, you have decided to base your design on NMOS logic, using a 3-input NOR gate as your basic building block, as shown below.

Each gate uses three 2N7000 N-channel MOSFETs as pulldown transistors, and a 10K resistor as a passive pullup. You figure that you’ll need somewhere between 500 and 1000 of these gates to build a useful computer — after all, the original PDP-8 12-bit minicomputer CPU was built with only about 519 gates.

Approximately how fast will you be able to clock this computer?

Answer 1: The timing will depend primarily on the capacitive load on each logic gate, which would include both the wiring capacitance and the capacitance of the MOSFET gate(s) you’re driving.

For example, the 2N7000 has an input capacitance of 20 pF typical (50 pF max). If your average fanout is 3, plus some wiring capacitance, that gives you a typical load of 100 – 200 pF. With a 10K pullup, that gives you an R-C time constant of 1 – 2 µs. You’d probably need to allow at least two time constants for one “gate delay” for reliable switching, so we’re talking about 2 – 4 µs per gate.

To get useful work done, you’ll need to allow some maximum number of gate delays per clock period. This will depend on your specific design, but a number like 6 to 10 would be typical. So now we’re talking about a clock period of 12 – 40 µs, or frequencies in the range of 25 – 80 kHz.

Switching to a 1K pullup resistor would allow the frequency to scale up by roughly a factor of 10.

Problem 2: Assuming a supply voltage of 5V, about how much power would you expect this computer to consume?

Answer 2: You can assume that roughly half of the gates will be active (outputs low) at any given moment, with current passing through their pullup resistors. Each resistor passes 5V / 10K = 0.5mA, and if there are 1000 gates, this represents an worst-caxse current of 0.5A, giving a power consumption of 5V × 0.5A = 2.5W. If only about half the gates are active, then the average power will be about 1.25W.

Switching to a 1K pullup resistor will raise this average static power consumption to roughly 12.5W (5A, or 25W, worst-case).

Problem 3: How many 3-input gates does it take to construct a edge-triggered (master-slave) D flip-flop?

Answer 3: Six 3-input NOR gates can be used to build a master-slave D flip-flop.

Note that the active edge of the clock is the falling edge.

Problem 4: What famous computer was built using NOR gates exclusively for the logic?

Answer 4: The original Cray-1 supercomputer was constructed using a single type of IC for the logic that contained one 4-input and one 5-input NOR gate. This IC used ECL (emitter-coupled logic) technology and the machine ran with a cycle time of 12.5 ns (80 MHz). About 200,000 gates were required to implement the CPU.

**Contributor:** David Tweed