#### Answer 2—The circuit generates rising edges (also falling edges) at intervals of 4 clocks, 4 clocks and 5 clocks, but the ideal spacing would be 4.3333 clocks. Therefore two of the intervals are short by 1/3 clock and one of them is long by 2/3 clock.

Therefore, the cycle-to-cycle peak-to-peak jitter is 1/3 + 2/3 = 1 full input clock period, or 62.5 ns. But taking an average over a complete group of 13 clocks, no edge is displaced from its “ideal” location by more than 1/3 clock, or 20.8 ns.

#### Answer 3—The following table shows the divider ratios required for various standard baud rates.

As you can see, a modern UART can generate the clocks for baud rates up to 38400 with the exact same error as the 3/13 counter scheme — note that 26 and 52 are multiples of 13. But above that, the frequency error increases. This is why microcontrollers with built-in UARTs often run at “oddball” frequencies such as 11.0592 MHz or 12.288 MHz — these freqeuncies can be easily divided down to produce precisely correct baud rates.