The Future of Nanotube Computing

For decades, silicon-based transistors have been the workhorse of the semiconductor industry, achieving remarkable advances in computational power. While advances continue to be made, alternative technologies are being explored to increase computational power and efficiency beyond the limits of silicon.

Carbon nanotubes (CNTs) are nanocylinders of carbon atoms, approximately 1 nm in diameter. They have amazing electrical, thermal, and physical properties. CNTs can be used to form CNT field-effect transistors (CNFETs), which use CNTs as the channel material of the transistor, with traditional lithographically defined sources, drains, and gates. It has been projected that digital systems made from carbon nanotubes can achieve more than an order of magnitude benefit in energy delay product (a common metric to compare a circuit’s performance and energy efficiency) compared to competing technologies.

However, it has been impracticable to realize these system-level benefits due to the inability to manufacture CNT-based circuits. This limitation stems from substantial imperfections inherent with the CNTs, including mispositioned and metallic CNTs. Mispositioned CNTs cause erroneous connections in a circuit, metallic (rather than semiconducting) CNTs decrease Ion/Ioff ratio, both potentially resulting in incorrect logic functionality and power wastage.

The trivial solution to these obstacles is to grow 100% perfectly aligned and semiconducting CNTs. However, this is currently infeasible, and likely never will be. Thus, to overcome these inherent imperfections, our Stanford University research team uses the imperfection-immune design paradigm. This paradigm combines processing solutions and design “tricks” to overcome these imperfections in the very-large-scale integration (VLSI) compatible manner.

Max Shulaker, a graduate student at Stanford University and author of this essay, holds a wafer filled with CNTs. (Photo: Norbert von der Groeben )

Max Shulaker, a graduate student at Stanford University and author of this essay, holds a wafer filled with CNTs. (Photo credit: Norbert von der Groeben )

We begin by growing the CNTs highly aligned. This is accomplished by growing the CNTs on a crystalline quartz substrate. The CNTs grow along the crystalline boundary of the quartz and result in highly aligned growths—99.5% alignment. However, for VLSI applications, there are millions or billions of transistors, resulting in billions of CNTs. Thus 99.5% is insufficient.

In addition, we employ mispositioned CNT immune design, which is a technique that renders the circuits that we make 100% immune to any mispositioned CNTs that would be left on the wafer. An important point is that the design is not dependent on the exact placement of the individual CNTs. It works for any arbitrary configuration of CNTs, and thus is manufacturable and scalable to very-large-scale circuits.

To remove metallic CNTs, we break them down, much like a fuse. We turn off all semiconducting CNTs in the circuit and pulse a large voltage across the transistors. Only the metallic CNTs conduct current, and by passing enough current, eventually heat up to

Max M. Shulaker, who holds a wafer filled with carbon nanotubes (CNTs), is a PhD candidate at Stanford University where he earned his BS in Electrical Engineering. He is part of a Stanford research team that recently built the first functioning computer using CNTs. Max works on experimentally demonstrating nanosystems with emerging technologies. His current research focuses on realizing increased levels of integration for CNT-based digital logic circuits. (Photo credit: Norbert von der Groeben)

Max M. Shulaker, who wrote this essay for Circuit Cellar, holds a wafer filled with carbon nanotubes (CNTs). Max is a PhD candidate at Stanford University where he earned his BS in Electrical Engineering. He is part of a Stanford research team that recently built the first functioning computer using CNTs. Max works on experimentally demonstrating nanosystems with emerging technologies. His current research focuses on realizing increased levels of integration for CNT-based digital logic circuits. (Photo credit: Norbert von der Groeben)

the point where they break down, much like a fuse. The trick is being able to perform this breakdown at a chip  scale. Computers today have billions of transistors. It would be infeasible to breakdown each transistor one by one. VLSI-compatible metallic CNT removal (VMR) is a design technique that enables the breakdown to be performed at an entire chip scale.

The imperfection-immune design paradigm, coupled with CNT-specific fabrication processing resulting in high-yield devices, permits, for the first time, the realization of larger-scale digital systems using this very promising technology. Most recently, a basic computer was fabricated at Stanford University completely using CNFETs. The CNT computer was composed of tens of thousands of CNTs, demonstrating the ability to manufacture CNT circuits in a scalable, and thus manufacturable, manner. The computer executes the subtract and branch if negative (SUBNEG) instruction, which is Turing complete, adding to the computer’s generality. As a demonstration, the CNT computer concurrently counted integers and sorted integers, continuously swapping between the two processes. To demonstrate the computer’s flexibility, it also emulated 20 different instructions from the commercial MIPS instruction set.

The CNT computer, culminating years of work by a team of researchers at Stanford University led by Professors Subhasish Mitra and Philip Wong, demonstrates that CNTs are a manufacturable and feasible technology. Beyond CNTs, it is a step forward for the broader field of emerging nanotechnologies. While many alternatives to silicon are being explored, the CNT computer represents an initial demonstration of one of these emerging technologies coming to fruition.

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