Myth Busted: The Truth About Developing Embedded Vision Solutions

Are embedded vision solutions complex? Expensive? Strictly about software? Get answers to your top questions about developing embedded vision solutions, right from Avnet & Xilinx.

We’re at the moment of truth with embedded vision systems as scores of new applications means designs must go up faster than ever—with new technologies dropping every day.

But isn’t embedded vision complex? Lacking scalability? Rigid in its design capability?

Truth be told, most of those ideas are myths. From the development of the first commercially viable FPGA in the 1980s to now, the amount of progress that’s been made has revolutionized the space.

So while it can be complex to decide how you’ll enter an ever-changing embedded vision market, it’s simpler than it used to be. It’s true: Real-time object detection used to be a strictly research enterprise and image processing a solely software play. Today, though, All Programmable devices enable system architects to create embedded vision solutions in record time.

As far as flexibility goes, you’ll find something quite similar. In the past, programming happened on the software side because hardware was preformatted. But FPGAs are more customizable. They contain logic blocks, the programmable components and reconfigurable interconnects that allow the chip to be programmed which allows for more efficiency of power, temperature and design—all without the need of an additional OS.

Ready to bust some more myths around embedded vision? Watch our video breaking down the five biggest myths around embedded vision development.


Kintex Ultrascale FPGA-Based Cards Target Radar, Comms

Pentek has ntroduced the newest member of the Jade family of high-performance data converter XMC modules based on the Xilinx Kintex Ultrascale FPGA. The Model 71141 is a 6.4 GHz dual channel analog-to-digital and digital-to-analog converter with programmable DDCs (digital downconverters) and DUCs (digital upconverters). The Model 71141 is suitable for connection to IF or RF signals for very wideband communications or radar system applications including:

  • Satellite communications (SATCOM)
  • Phased array radar, SIGINT and ELINT
  • Synthetic aperture radar (SAR)71141
  • Time-of-flight and LIDAR distance measurement
  • RF sampling software defined radio (SDR)

For applications that require unique functions, users can install custom IP for specialized data processing tasks. Pentek’s Navigator FPGA Design Kit includes source code for all factory-installed IP modules. Developers can integrate their own IP with the Pentek functions or use the Navigator kit to completely replace the Pentek IP with their own.

The Pentek Navigator tools reduce the development time and cost associated with complex designs. Users can also select the size of the FPGA they would like installed so they are getting exactly what they need performance-wise without paying for a larger FPGA they may not need. Unlike others in the industry, Pentek still provides application support to customers at no cost.

The Model 71141 is the first of the Pentek Jade products to use the Texas Instruments ADC12DJ3200 12-bit A/D. The front end accepts analog RF inputs on a pair of front panel SSMC connectors. The converter operates in single-channel interleaved mode with a sampling rate of 6.4 GS/sec and an input bandwidth of 7.9 GHz; or, in dual-channel mode with a sampling rate of 3.2 GS/sec and input bandwidth of 8.1 GHz.

The A/D built-in digital down converters support 2x decimation in real output mode and 4x, 8x or 16x decimation in complex output mode. The A/D digital outputs are delivered into the FPGA for signal processing, data capture or for routing to other module resources.

A Texas Instruments DAC38RF82 D/A with DUC accepts a baseband real or complex data stream from the FPGA and provides that input to the upconversion, interpolation and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals. It delivers real or quadrature (I+Q) analog outputs to the dual 14-bit D/A converter. The two 6.4 GS/sec 14-bit D/As pair well with the dual input channels while delivering more than twice the output performance of previous generations of Pentek products.

The 71141 factory-installed functions include two A/D acquisition and two D/A waveform generation IP modules. In addition, IP modules for DDR4 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe Gen.3 interface complete the factory-installed functions. System integrators get to market with less time and risk, because the 71141 delivers a complete turnkey solution without the need to develop any FPGA IP.

The Pentek Jade Architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50% with equally impressive reductions in cost, power dissipation and weight. As the central feature of the Jade Architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. A 5 GB bank of DDR4 SDRAM is available to the FPGA for custom applications. The x8 PCIe Gen 3 link can sustain 6.4 GB/s data transfers to system memory. Eight additional gigabit serial lanes and LVDS general-purpose I/O lines are available for custom solutions.

The Model 71141 XMC module is designed to operate with a wide range of carrier boards in PCIe, 3U and 6U VPX, AMC, and 3U and 6U CompactPCI form factors, with versions for both commercial and rugged environments. Designed for air-cooled, conduction-cooled and rugged operating environments, the Model 71141 XMC module with 5 GB of DDR4 SDRAM starts at $18,795. Additional FPGA options are available. The Navigator Design Suite consists of two packages. The Navigator BSP is $2,500 and the Navigator FDK is $3,500.

Pentek |

New FPGA Board Based on the Xilinx UltraScale VU190 Device

BittWare recently released a new COTS PCIe board based on Xilinx’s 20-nm UltraScale VU190 FPGA. The XUSP3R is a 3/4-length PCIe board offers up to four Gen3 x8 PCIe interfaces, along with four front panel QSFP28 cages, supporting 16 lanes of 25 Gbps or 4 lanes of 100 Gbps, including 100 GbE. Four DIMM sockets support massive memory configurations including up to 256 GB of DDR4 memory across four 72-bit wide banks.

Alternatively, each DIMM socket can be populated with BittWare’s dual bank QDR DIMMs, each providing 576 Mb of QDR-II+. An optional Hybrid Memory Cube (HMC) module with up to 4 GB is also available that can be populated in addition to, and independent of, the DIMMs. Together, these features make the XUSP3R well suited for a variety of data center and networking applications, including compute acceleration, network processing, cybersecurity, and storage.

The board also offers features and tools for simplified development and integration. A comprehensive Board Management Controller (BMC) with host software support for advanced system monitoring simplifies platform management. A complete software tool suite and FPGA development/project examples are also available.

The XUSP3R’s features and specs:

  • High-performance Xilinx Virtex UltraScale 190/160/125
  • Up to four independent PCIe Gen3 x8 interfaces
  • Four QSFP28 cages for 4x 100GbE, 16x 25GbE, 4x 40GbE, or 16x 10GbE (or combinations thereof)
  • Four DIMM sites that support DDR4-2133 SDRAM, QDR-IV, and QDR-II+
  • Optional HMC Module (in addition to, and independent of, the DIMM sites)
  • Board Management Controller for Intelligent Platform Management
  • USB 2.0 for programming, debug, or control with optional integrated Platform Cable USB functionality
  • Timestamping and synchronization support
  • Complete software support with BittWare’s BittWorks II Toolkit
  • FPGA development kit for FPGA board support IP and integration

The XUSP3R board is in production and shipping now. Contact BittWare for more details and pricing.

Source: BittWare

New Dev Kit for Xilinx FPGA-Enabled Accelerator Cards

BittWare recently announced upcoming availability of an OpenPOWER CAPI Developer’s Kit for its Xilinx FPGA-enabled accelerator cards. The kit is intended to give you a fast way to connect the Xilinx All Programmable FPGA to a CAPI-enabled IBM POWER8 system.

The kit includes:

  • BittWare XUSP3S FPGA accelerator card, which is a ¾-length PCIe board featuring the Xilinx Virtex UltraScale VU095, four QSFPs for 4× 100 GbE, and flexible memory configurations with up to 64 GB of memory and support for Hybrid Memory Cube (HMC)
  • IBM Power Service Layer (PSL) IP to provide the connection to the POWER8 chip
  • CAPI host support library
  • An example CAPI design


BittWare’s OpenPOWER CAPI Developer’s Kit is scheduled to be available in Q2 2016.

Source: BittWare

ZestET2-NJ Gigabit Ethernet FPGA Module

Orange Tree Technologies recently launched the ZestET2-NJ high-performance Gigabit Ethernet FPGA module, which comprises a Gigabit Ethernet processing engine, Xilinx Artix-7 FPGA, DDR3 memory, and general-purpose I/O. Delivering the maximum sustained Ethernet bandwidth of over 100 MBps in both directions simultaneously, it is aimed at data acquisition and control applications in markets such as industrial vision, radar, sonar and medical imaging.OrangeTree-zestet2-nj

The Xilinx Artix-7 XC7A35T FPGA, which has more than 33,000 logic cells, 1.8 Mb of Block RAM and 90 DSP slices, is tightly coupled with 512 MB of 400-MHz DDR3 SDRAM, giving it an ample memory bandwidth of 1.6 GBps for high-speed processing and formatting of streaming data.  With ease of integration in mind, there are 105 FPGA I/O pins available for connection to the user’s equipment.

Orange Tree’s proprietary GigEx chip handles the entire TCP/IP stack at over 100 MBps in each direction simultaneously. It enables the User FPGA to be dedicated entirely to the application for maximum efficiency.  The module measures just 40 × 50 mm, making it ideal for integration into your products.

Source: Orange Tree Technologies

Kernel RTOS Evaluation Kit

eSOL has started offering the eT-Kernel Evaluation Kit for Xilinx’s Zynq-7000 All Programmable SoC, which combines the dual-core ARM Cortex-A9 MPCore processor with Xilinx’s 28-nm programmable logic fabric. The Evaluation Kit integrates eSOL’s eT-Kernel Multi-Core Edition real time operating system (RTOS), its dedicated eBinder integrated development environment (IDE), middleware components, and device drivers. This complimentary 30-day Evaluation Kit permits developers to easily and quickly evaluate the performance and quality of Xilinx Zynq-7000 All Programmable SoC and eT-Kernel. Since eT-Kernel inherited the functions and architecture of uITRON, the most popular RTOS in Japan and Asian countries, developers can reuse their uITRON-based software assets without further work.

Run-time software in the Evaluation Kit includes the eT-Kernel Multi-core Edition, eSOL’s PrFILE2 FAT file system, the SD memory card driver, and the HDMI display driver, all of which are integrated and immediately run on the Zynq-7000 All Programmable SoC Evaluation Board. The eBinder IDE is available for eT-Kernel Multi-Core Edition-based software development. Besides ARM’s genuine compiler, eBinder offers various development tools and functions to strongly support multi-programming, debugging, and analysis for complex multi-core software development.

Zynq-7000 All Programmable SoC tightly integrates two ARM Cortex-A9 MPCore processors and FPGA fabric. The hardware and software programmability of Zynq-7000 AP SoC enables system development with high performance, flexibility, and scalability, while achieving lower power consumption and cost.

The eT-Kernel/Zynq-7000 All Programmable SoC Evaluation Kit allows developers to jump-start their evaluation using packaged device drivers, which saves the time and money of developing them. Zynq-7000 All Programmable SoC and the eT-Kernel Platform are an ideal combination for advanced embedded systems in the automotive, industrial, and medical arenas, including Automotive Driver Assistance Systems (ADAS), high-resolution graphic systems, machine vision systems, and network systems.

[Source: eSOL Co., Ltd]

Embedded SOM with Linux-Based RTOS

National Instruments has introduced an embedded system-on-module (SOM) development board with integrated Linux-based real-time operating system (RTOS).NIsom

Processing power in the 2” x 3” SOM comes from a Xilinx Zync-7020 all programmable SOC running a dual core ARM Cortex-A9 at 667 MHz. A built-in, low-power Artix-7 FPGA offers 160 single-ended I/Os and Its dedicated processor I/O include Gigabit Ethernet USB 2.0 host, USB 2.0 host/device, SDHC, RS-232, and Tx/Rx. The SOM’s power requirements are typically 3 to 5 W.

The SOM integrates a validated board support package (BSP) and device drivers together with the National Instruments Linux real-time OS. The SOM board is supplied with a full suite of middleware for developing an embedded OS, custom software drivers, and other common software components.

The LabVIEW FPGA graphical development platform eliminates the need for expertise in the design approach using a hardware description language.

[Via Elektor]


All-Programmable SoC Solution

Anyone creating a complex, powerful digital design may want to turn to a single device that integrates high-speed processing and programmable logic.

In Circuit Cellar’s April issue, columnist Colin O’Flynn explores using the Xilinx Zynq  Z-7020 All Programmable SoC (system-on-a-chip) as part of the Avnet ZedBoard development board.

“I used a Xilinx Zynq SoC device, although Altera offers several flavors of a similar device (e.g., the Cyclone V SoC, the Arria V SoC, and the Arria 10 SoC), and Microsemi offers the SmartFusion2 SoC FPGA,” O’Flynn says in his article. “The Xilinx and Altera devices feature a dual-core ARM Cortex-A9 processor, whereas the Microsemi devices feature a less powerful Cortex-M3 processor. You may not need a dual-core A9 processor, so ‘less powerful’ may be an advantage.”

While O’Flynn’s article introduces the ZedBoard, he notes many of its specifics also apply to the MicroZed board, a less expensive option with a smaller SoC. Xilinx’s Zynq device has many interesting applications made highly accessible through the ZedBoard and MicroZed boards, he says.

O’Flynn’s discussion of the Zynq SoC device includes the following excerpt. (The April issue, which includes O’Flynn’s full article, is available for membership download or single-issue purchase.)

Originally, I had planned to describe a complete demo project in this article. I was going to demonstrate how to use a combination of a custom peripheral and some of the hard cores to stream data from a parallel ADC device into DDR memory. But there wasn’t enough room to introduce the tools and cover the demo, so I decided to introduce the Zynq device (using the ZedBoard).

A demo project is available at Several tutorials for the Zynq device are available at and, so there isn’t any point in duplicating work! I’ve linked to some specific tutorials from the April 2014 post on Photo 1 shows the hardware I used, which includes a ZedBoard with my custom OpenADC board connected through the I/O lines.

An Avnet ZedBoard is connected to the OpenADC. The OpenADC provides a moderate-speed ADC (105 msps), which interfaces to the programmable logic (PL) fabric in Xilinx’s Zynq device via a parallel data bus. The PL fabric then maps itself as a peripheral on the hard-core processing system (PS) in the Zynq device to stream this data into the system DDR memory.

Photo 1: An Avnet ZedBoard is connected to the OpenADC. The OpenADC provides a moderate-speed ADC (105 msps), which interfaces to the programmable logic (PL) fabric in Xilinx’s Zynq device via a parallel data bus. The PL fabric then maps itself as a peripheral on the hard-core processing system (PS) in the Zynq device to stream this data into the system DDR memory.

Even if you’re experienced in FPGA design, you may not have used Xilinx tools for processor-specific design. These tools include the Xilinx Platform Studio (XPS) and the Xilinx Software Development Kit (SDK). Before the advent of hard-core processors (e.g., Zynq), there have long existed soft-core processors, including the popular Xilinx MicroBlaze soft processor. The MicroBlaze system is completely soft core, so you can use the XPS tool to define the peripherals you wish to include. For the Zynq device, several hard-core peripherals are always present and you can choose to add additional soft-core (i.e., use the FPGA fabric) peripherals.

In a future article I will discuss different soft-core processor options, including some open-source third-party ones that can be programmed from the Arduino environment. For now, I’ll examine only the Xilinx tools, which are applicable to the Zynq device, along with the MicroBlaze core.

The ARM cores in the Zynq device are well suited to run Linux, which gives you a large range of existing code and tools to use in your overall solution. If you don’t need those tools, you can always run on “bare metal” (e.g., without Linux), as the tools will generate a complete base project for you that compiles and tests the peripherals (e.g., printing “Hello World” out the USART). To give you a taste of this, I’ve posted a demo video of bringing up a simple “Hello World” project in both Linux and bare metal systems on

The FPGA part of the Zynq device is called the programmable logic (PL) portion. The ARM side is called the processing system (PS) portion. You will find a reference to the SoC’s PL or PS portion throughout most of the tutorials (along with this article), so it’s important to remember which is which!

For either system, you’ll be starting with the XPS software (see Photo 2). This software is used to design your hardware platform (i.e., the PL fabric), but it also gives you some customization of the PS hard-core peripherals.

This is the main screen of the Xilinx Platform Studio (XPS) when configuring a Zynq design. On the left you can see the list of available soft-core peripherals to add to the design. You can configure any of the hard-core peripherals by choosing to enable or disable them, along with selecting from various possible I/O connections. Additional screens (not shown) enable you to configure peripherals addressing information, configure I/O connections for the soft-core peripherals, and connect peripherals to various available extension buses.

Photo 2: This is the main screen of the Xilinx Platform Studio (XPS) when configuring a Zynq design. On the left you can see the list of available soft-core peripherals to add to the design. You can configure any of the hard-core peripherals by choosing to enable or disable them, along with selecting from various possible I/O connections. Additional screens (not shown) enable you to configure peripherals addressing information, configure I/O connections for the soft-core peripherals, and connect peripherals to various available extension buses.

For example, clicking on the list of hard-core peripherals opens the options dialogue so you can enable or disable each peripheral along with routing the I/O connections. The ZedBoard’s Zynq device has 54 multipurpose I/O (MIO) lines that can be used by the peripherals, which are split into two banks. Each bank can use different I/O standards (e.g., 3.3 and 1.5 V).

Enabling all the peripherals would take a lot more than 54 I/O lines. Therefore, most of the I/O lines share multiple functions on the assumption that every peripheral doesn’t need to be connected. Many of the peripherals can be connected to several different I/O locations, so you (hopefully) don’t run into two peripherals needing the same I/O pin.

Almost all of the peripheral outputs can be routed to the PL fabric as well under the name EMIO, which is a dedicated 64-bit bus that connects to the PL fabric. If you simply wish to get more I/O pins, you can configure these extra pins from within XPS. But you can also use this EMIO bus to control existing cores in your FPGA fabric using peripherals on the Zynq device.

Assume you had an existing FPGA design where you had an FPGA core doing some processing connected to a microcontroller or computer via I2C, SPI, or serial. You could simply connect this core to the appropriate PS peripheral and port the existing code onto the Zynq processor by changing the low-level calls to use the Zynq peripherals. You may eventually wish to change this interface to the peripheral bus, the AMBA Advanced eXtensible Interface (AXI), for better performance. However, using standard peripherals to interface to a PL design can still be useful for many cores for which you have extensive existing code.

The MIO/EMIO pins can even be used in a bit-banging fashion, so if you need a special device or core control logic, it’s possible to quickly develop this in software. You can then move to a hardware peripheral for considerably better performance.

O’Flynn’s article goes on to discuss in greater detail the internal buses, peripherals, and taking a design from hardware to software. For more, refer to Circuit Cellar‘s  April issue and related application notes posted at O’Flynn’s companion site

Embedded Programming: Rummage Around In This Toolbox

Circuit Cellar’s April issue is nothing less than an embedded programming toolbox. Inside you’ll find tips, tools, and online resources to help you do everything from building a simple tracing system that can debug a small embedded system to designing with a complex system-on-a-chip (SoC) that combines programmable logic and high-speed processors.

Article contributor Thiadmer Riemersma describes the three parts of his tracing system: a set of macros to include in the source files of a device under test (DUT), a PC workstation viewer that displays retrieved trace data, and a USB dongle that interfaces the DUT with the workstation (p. 26).

Thaidmer Riemersma's trace dongle is connected to a laptop and device. The dongle decodes the signal and forwards it as serial data from a virtual RS-232 port to the workstation.

Thaidmer Riemersma’s trace dongle is connected to a laptop and DUT. The dongle decodes the signal and forwards it as serial data from a virtual RS-232 port to the workstation.

Riemersma’s special serial protocol overcomes common challenges of tracing small embedded devices, which typically have limited-performance microcontrollers and scarce interfaces. His system uses a single I/O and keeps it from bottlenecking by sending DUT-to-workstation trace transmissions as compact binary messages. “The trace viewer (or trace “listener”) can translate these message IDs back to the human-readable strings,” he says.

But let’s move on from discussing a single I/0 to a tool that offers hundreds of I/0s. They’re part of the all-programmable Xilinx Zynq SoC, an example of a device that blends a large FPGA fabric with a powerful processing core. Columnist Colin O’Flynn explores using the Zynq SoC as part of the Avnet ZedBoard development board (p. 46). “Xilinx’s Zynq device has many interesting applications,” O’Flynn concludes. “This is made highly accessible by the ZedBoard and MicroZed boards.”

An Avnet ZedBoard is connected to the OpenADC. The OpenADC provides a moderate-speed ADC (105 msps), which interfaces to the programmable logic (PL) fabric in Xilinx’s Zynq device via a parallel data bus. The PL fabric then maps itself as a peripheral on the hard-core processing system (PS) in the Zynq device to stream this data into the system DDR memory.

An Avnet ZedBoard is connected to the OpenADC. (Source: C. O’Flynn, Circuit Cellar 285)

Our embedded programming issue also includes George Novacek’s article on design-level software safety analysis, which helps avert hazards that can damage an embedded controller (p. 39). Bob Japenga discusses specialized file systems essential to Linux and a helpful networking protocol (p. 52).

One of the final steps is mounting the servomotor for rudder control. Thin cords connect the servomotor horn and the rudder. Two metal springs balance mechanical tolerances.

Jens Altenburg’s project

Other issue highlights include projects that are fun as well as instructive. For example, Jens Altenburg added an MCU, GPS, flight simulation, sensors, and more to a compass-controlled glider design he found in a 1930s paperback (p. 32). Columnist Jeff Bachiochi introduces the possibilities of programmable RGB LED strips (p. 66).