Multi-Range Programmable DC Power Supplies

B&K9115_leftB&K Precision expanded its 9115 series with the addition of two new multi-range programmable DC power supplies: the 9115-AT and the 9116. Similar to the 9115, the new models deliver full 1,200-W output power in any combination of voltage and current within the rated limits. The models offer the same features as the 9115, but with a few differences.

The 9115-AT provides unique built-in automotive test functions that can simulate common test conditions to ensure reliability of electrical and electronic devices installed in automobiles. The 9116 offers a higher voltage range up to 150 V. Both models are suitable for automotive and a variety of benchtop or automated test equipment (ATE) system applications.

B&K9116_rearThe 9115-AT and the 9116 include a high-resolution vacuum fluorescent display (VFD), independent voltage and current control knobs, cursors, and a numerical keypad for direct data entry. Both models also provide internal memory storage to save and recall up to 100 different instrument settings, sequence (list mode) programming, and configurable overvoltage and overpower protection limits. The 9115 series offers remote control software for front-panel emulation, generation and execution of test sequences, and logging measurements via a PC.

The 9115-AT and 9116 cost $2,345 and $1,995, respectively.

B&K Precision Corp.
www.bkprecision.com

Low-Power AC Input LED Drivers

XPThe DLE25 and DLE35 series of AC input LED drivers incorporate universal input with active power factor correction in a two-power stage design to eliminate flicker while providing a high-efficiency solution. The series includes dimmable constant current versions with PWM, voltage, and resistance programming capabilities.

The DLE25 and DLE35 drivers are packaged in an IP67-rated 3.68“ × 2.89“ × 1.29“ enclosure and are waterproof to depths up to 1 m, making them suitable for use in almost any outdoor application. Typical operating efficiency is in the 78% to 83% range.

Accommodating the extended universal input voltage range from 90 to 305 VAC, the DLE series supports the 277 VAC system used in the US. The series complies with EN61347 and UL8750 safety approvals and Class B conducted and radiated noise limits as specified by EN55015.

The DLE25 series costs $21.06 in 500-piece quantities.

XP Power, Ltd.
www.xppower.com

Issue 286: EQ Answers

Question 1—A divider is a logic module that takes two binary numbers and produces their numerical quotient (and optionally, the remainder). The basic structure is a series of subtractions and multiplexers, where the multiplexer uses the result of the subtraciton to select the value that gets passed to the next step. The quotient is formed from the bits used to control the multiplexers, and the remainder is the result of the last subtraction.

If it is implemented purely combinatorially, then the critical path through all of this logic is quite long (even with carry-lookahead in the subtractors) and the clock cycle must be very slow. What could be done to shorten the clock period without losing the ability to get a result on every clock?

Answer 1—Pretty much any large chunk of combinatorial logic can be pipelined in order to reduce the clock period. This allows it to produce more results in a given amount of time, at the expense of increasing the latency for any particular result.

Divider logic is very easy to pipeline, and the number of pipeline stages you can use is fairly arbitrary. You could insert a pipeline register after each subtract-mux pair, or you might choose to do two or more subtract-mux stages per pipeline register You could even go so far as to pipeline the subtracts and the muxes separately (or even pipeline *within* each subtract) in order to get the fastest possible clock speed, but this would be rather extreme.

The more pipeline registers you use, the shorter the critical path (and the clock period) can be, but you use more resources (the registers). Also, the overall latency goes up, since you need to account for the setup and propagation times of the pipeline registers in the clock period (in addition to the subtract-mux logic delays). This gets multiplied by the number of pipeline stages in order to compute the total latency.

Question 2—On the other hand, what could be done to reduce the amount of logic required for the divider, giving up the ability to have a result on every clock?

 

Answer 2—If you don’t need the level of performance provided by a pipelined divider, you can computes the quotient serially, one bit at a time. You would just need one subtractor and one multiplexer, along with registers to hold the input values, quotient bits and the intermediate result.

You could potentially compute more than one bit per clock period using additional subtract-mux stages. This gives you the flexibility to trade off space and time as needed for a particular application.

Question 3—An engineer wanted to build an 8-MHz filter that had a very narrow bandwidth, so he used a crystal lattice filter like this:

EQ-fig1-CC287-June14

However, when he built and tested his filter, he discovered that while it worked fine around 8 MHz, the attenuation at very high frequencies (e.g., >80 MHz) was very much reduced. What caused this?

Answer 3—The equivalent circuit for a quartz crystal is something like this:EQ-fig2-CC287-June14

The components across the bottom represent the mechanical resonance of the crystal itself, while the capacitor at the top represents the capacitance of the electrodes and holder. Typical values are:

  • Cser: 10s of fF (yes, femtofarads, 10-15F)
  • L: 10s of mH
  • R: 10s of ohms
  • Cpar: 10s of pF

The crystal has a series-resonant frequency based on just Cser and L. It has a relatively low impedance (basically just R) at this frequency.

It also has a parallel-resonant (sometimes called “antiresonant”) frequency when you consider the entire loop, including Cpar. Since Cser and Cpar are essentially in series, together they have a slightly lower capacitance than Cser alone, so the parallel-resonant frequency is slightly higher. The crystal’s impedance is very high at this frequency.

But at frequencies much higher than either of the resonant frequencies, you can see that the impedance of Cparalone dominates, and this just keeps decreasing with increasing frequency. This reduces the crystal lattice filter to a simple capacitive divider, which passes high freqeuncies with little attenuation.

Question 4—Suppose you know that a nominal 10.000 MHz crystal has a series-resonant frequency of 9.996490 MHz and a parallel-resonant frequency of 10.017730 MHz. You also know that its equivalent series capacitance is 27.1 fF. How can you calculate the value of its parallel capacitance?

Answer 4—First, calculate the crystal’s equivalent inductance, based on the series-resonant frequency:EQ-equation1-CC287-June14

Next, calculate the capacitance required to resonate with that inductance at the parallel-resonant frequency:EQ-equation2-CC287-June14

Finally, calculate the value of Cpar required to give that value of capacitance when in series with Cser:EQ-equation3-CC287-June14

Note that all three equations can be combined into one, and this reduces to:EQ-equation4-CC287-June14

Issue 284: EQ Answers

PROBLEM 1
Can you name all of the signals in the original 25-pin RS-232 connector?

ANSWER 1
Pins 9, 10, 11, 18, and 25 are unassigned/reserved. The rest are:

Pin Abbreviation Source Description
1 PG - Protective ground
2 TD DTE Transmitted data
3 RD DCE Received data
4 RTS DTE Request to send
5 CTS DCE Clear to send
6 DSR DCE Data Set Ready
7 SG - Signal ground
8 CD DCE Carrier detect
12 SCD DCE Secondary carrier detect
13 SCTS DCE Secondary clear to send
14 STD DTE Secondary transmitted data
15 TC DCE Transmitter clock
16 SRD DCE Secondary received data
17 RC DCE Receiver clock
19 SRTS DTE Secondary request to send
20 DTR DTE Data terminal ready
21 SQ DCE Signal quality
22 RI DCE Ring indicator
23 - DTE Data rate selector
24 ETC DTE External transmitter clock

 

PROBLEM 2
What is the key difference between a Moore state machine and a Mealy state machine?

ANSWER 2
The key difference between Moore and Mealy is that in a Moore state machine, the outputs depend only on the current state, while in a Mealy state machine, the outputs can also be affected directly by the inputs.

 

PROBLEM 3
What are some practical reasons you might choose one state machine over the other?

ANSWER 3
In practice, the difference between Moore and Mealy in most situations is not very important. However, when you’re trying to optimize the design in certain ways, it sometimes is.

Generally speaking, a Mealy machine can have fewer state variables than the corresponding Moore machine, which will save physical resources on a chip. This can be important in low-power designs.

On the other hand, a Moore machine will typically have shorter logic paths between flip-flops (total combinatorial gate delays), which will enable it to run at a higher clock speed than the corresponding Mealy machine.

 

PROBLEM 4
What is the key feature that distinguishes a DSP from any other general-purpose CPU?

ANSWER 4
Usually, the key distinguishing feature of a DSP when compared with a general-purpose CPU is that the DSP can execute certain signal-processing operations with few, if any, CPU cycles wasted on instructions that do not compute results.

One of the most basic operations in many key DSP algorithms is the MAC (multiply-accumulate) operation, which is the fundamental step used in matrix dot and cross products, FIR and IIR filters, and fast Fourier transforms (FFTs). A DSP will typically have a register and/or memory organization and a data path that enables it to do at least 64 MAC operations (and often many more) on unique data pairs in a row without any clocks wasted on loop overhead or data movement. General-purpose CPUs do not generally have enough registers to accomplish this without using additional instructions to move data between registers and memory.

Experimenting with Dielectric Absorption

Dielectric absorption occurs when a capacitor that has been charged for a long time briefly retains a small amount of voltage after a discharge.

“The capacitor will have this small amount of voltage even if an attempt was made to fully discharge it,” according to the website wiseGEEK. “This effect usually lasts a few seconds to a few minutes.”

While it’s certainly best for capacitors to have zero voltage after discharge, they often retain a small amount through dielectric absorption—a phenomenon caused by polarization of the capacitor’s insulating material, according to the website. This voltage (also called soakage) is totally independent of capacity.

At the very least, soakage can impair the function of a circuit. In large capacitor systems, it can be a serious safety hazard.

But soakage has been around a long time, at least since the invention of the first simple capacitor, the Leyden jar, in 1775. So columnist Robert Lacoste decided to have some “fun” with it in Circuit Cellar’s February issue, where he writes about several of his experiments in detecting and measuring dielectric absorption.

Curious? Then consider following his instructions for a basic experiment:

Go down to your cellar, or your electronic playing area, and find the following: one large electrolytic capacitor (e.g., 2,200 µF or anything close, the less expensive the better), one low-value discharge resistor (100 Ω or so), one DC power supply (around 10 V, but this is not critical), one basic oscilloscope, two switches, and a couple of wires. If you don’t have an oscilloscope on hand, don’t panic, you could also use a hand-held digital multimeter with a pencil and paper, since the phenomenon I am showing is quite slow. The only requirement is that your multimeter must have a high-input impedance (1 MΩ would be minimum, 10 MΩ is better).

Figure 1: The setup for experimenting with dielectric absorption doesn’t require more than a capacitor, a resistor, some wires and switches, and a voltage measuring instrument.

Figure 1: The setup for experimenting with dielectric absorption doesn’t require more than a capacitor, a resistor, some wires and switches, and a voltage measuring instrument.

Figure 1 shows the setup. Connect the oscilloscope (or multimeter) to the capacitor. Connect the power supply to the capacitor through the first switch (S1) and then connect the discharge resistor to the capacitor through the second switch (S2). Both switches should be initially open. Photo 1 shows you my simple test configuration.

Now turn on S1. The voltage across the capacitor quickly reaches the power supply voltage. There is nothing fancy here. Start the oscilloscope’s voltage recording using a slow time base of 10 s or so. If you are using a multimeter, use a pen and paper to note the measured voltage. Then, after 10 s, disconnect the power supply by opening S1. The voltage across the capacitor should stay roughly constant as the capacitor is loaded and the losses are reasonably low.

Photo 1: My test bench includes an Agilent Technologies DSO-X-3024A oscilloscope, which is oversized for such an experiment.

Photo 1: My test bench includes an Agilent Technologies DSO-X-3024A oscilloscope, which is oversized for such an experiment.

Now switch on S2 long enough to fully discharge the capacitor through the 100-Ω resistor. As a result of the discharge, the voltage across the capacitor’s terminals will quickly become very low. The required duration for a full discharge is a function of the capacitor and resistor values, but with the proposed values of 2,200 µF and 100 Ω, the calculation shows that it will be lower than 1 mV after 2 s. If you leave S2 closed for 10 s, you will ensure the capacitor is fully discharged, right?

Now the fun part. After those 10 s, switch off S2, open your eyes, and wait. The capacitor is now open circuited, at least if the voltmeter or oscilloscope input current can be neglected, so the capacitor voltage should stay close to zero. But you will soon discover that this voltage slowly increases over time with an exponential shape.

Photo 2 shows the plot I got using my Agilent Technologies DSO-X 3024A digital oscilloscope. With the capacitor I used, the voltage went up to about 120 mV in 2 min, as if the capacitor was reloaded through another voltage source. What is going on here? There aren’t any aliens involved. You have just discovered a phenomenon called dielectric absorption!

Photo 2: I used a 2,200-µF capacitor, a 100-Ω discharge resistor, and a 10-s discharge duration to obtain this oscilloscope plot. After 2 min the voltage reached 119 mV due to the dielectric absorption effect.

Photo 2: I used a 2,200-µF capacitor, a 100-Ω discharge resistor, and a 10-s discharge duration to obtain this oscilloscope plot. After 2 min the voltage reached 119 mV due to the dielectric absorption effect.

Nothing in Lacoste’s column about experimenting with dielectric absorption is shocking (and that’s a good thing when you’re dealing with “hidden” voltage). But the column is certainly informative.

To learn more about dielectric absorption, what causes it, how to detect it, and its potential effects on electrical systems, check out Lacoste’s column in the February issue. The issue is now available for download by members or single-issue purchase.

Lacoste highly recommends another resource for readers interested in the topic.

“Bob Pease’s Electronic Design article ‘What’s All This Soakage Stuff Anyhow?’ provides a complete analysis of this phenomenon,” Lacoste says. “In particular, Pease reminds us that the model for a capacitor with dielectric absorption effect is a big capacitor in parallel with several small capacitors in series with various large resistors.”