Designing a Debug and Test Tool

While developing mixed signal IC products, I often longed for a personal, simple to use, analog and digital pattern generator tool. So after retiring, I decided to create one. Read how Validator 1, a USB benchtop debug and test tool, was developed.


 

by William Holt, retired founder of Holt IC

During a career largely spent developing mixed signal IC products, I often longed for a personal, simple to use, analog and digital pattern generator tool. Numerous occasions arose where it was necessary to check performance or parameters of an IC, a breadboard, or an application board. Sometimes the setup was trivial: a few supplies and a signal generator or two. And sometimes the setup was quite complex.  I had a few tools for the tougher problems but there was usually something not quite matching up – logic or interface voltages, offset, synchronization, limited pattern width or length, and limited pattern control options. After retiring, I looked for a project to fill the void and decided to take on the challenge of creating a personal debug and test tool.

The first step was to make a wish list for performance and functions:

  • 16 digital input / output (DIO) pins and 2 high voltage DACs
  • Able to interface with any digital voltage standard
  • run digital patterns from DC to 50 Mhz
  • have a pattern depth of at least 4 K per pin and up to 1,000 clocks at each pattern line
  • pattern controls for looping and branching
  • easily expandable to synchronously drive up to 64 channels in parallel
  • test any channel for its digital state at any time step and show where the fault is in the pattern
  • output arbitrary analog waveforms in the -10V to +10V range in sync with the digital
  • start patterns from either an edge or a button push
  • nonvolatile memory for standalone operation
  • easy to program
  • under $500

But first, why should I try to create such a tool if one is already available? There are indeed options to consider. Let’s take a closer look at some possibilities:

Off the Shelf Pattern Generators

A variety of commercial products could fulfill the digital pattern generator function and some include analog capability. However the “under $500” criteria eliminates most. The remaining options usually require converting the pattern to code if the pattern is large and complex. Some do provide software to input patterns via a timing diagram. Timing diagrams work fine for simple requirements.

Microcontrollers with GPIO and DACs

This option can work provided the output/input voltages available at the digital and analog pins are compatible with the DUT.  Manufacturers provide development boards and software that allow access to the GPIO pins and other peripheral assets. The issues are:

1. Getting significant pattern depth (memory) behind each pin
2. Finding an easy way to translate pattern into code.

FPGA

FPGAs can provide adequate memory bits behind each pin and a variety of on-chip resources.  If you are willing to spend the time to design the tool yourself, this path will work. Indeed, this became my solution. I embarked on a software / hardware design project to make a unique product called Validator 1

The Validator Pattern Generator Design

The hardware implementation of a digital and analog bit pattern generator is straightforward. Consider the architecture shown in the Block Diagram below. The basic output mechanism is to clock the memory address counter, read the next line of massively parallel memory bits, and feed the result to the outside world. The faster this path, the higher the maximum frequency. The data accessed with each read cycle is a line of pattern data.  Lines of pattern then correspond to a memory address.

Before a pattern can be run, we need a convenient way to load memory with the pattern. The method selected was by USB communication with a host program.

     

USB Interface

Setup and pattern data will be read from a CSV file and passed by host software, via USB, to pattern memory RAM and, simultaneously, to duplicate nonvolatile pattern memory RAM. The ideal design would combine both RAMs into one memory but issues with speed and available FPGA resources prohibit this option for now.

The 8051 microcontroller provides the USB interface. A host command initiates an 8051 sequence to convert the serial USB stream into 8 bit bytes which are transferred to the Memory Write State Machine by GPIO.   Additional GPIO pins signal start, finish, and byte order. The first bytes pass a code telling the State Machine whether this will be a memory load or alternatively, a command for the Pattern Control block, like Run or Reset.

The Auto Load Sequencer block provides the mechanism to read back nonvolatile memory into pattern memory when initiated by a Load button closure. This fulfills the goal of standalone operation. Data flow to the State Machine from nonvolatile memory is identical to a USB download from the 8051.

The Periodic Status Transmit block creates a serial UART string at set intervals and sends it to the 8051.   This string is coded to display the status, address, and fail channels on the host program control panel. The 8051 automatically passes it by USB to the host.

Setup Memory block

Each pattern load starts with a string of Setup Data for these setup choices:

Select External or Internal Clock
Select Clock division from 1 to 1024 (0 equals divide by 1,000,000)
Select whether to start on a SYNC input edge or on the Run button closure
Select which SYNC edge, positive or negative
Select whether to stop the pattern immediately on any Fail condition
Select whether to output the internal clock at the EXT CLK input (provide a clock source for parallel units)

Jump Address Memory block

The pattern memory address counter can be jammed with a Jump address. The CSV file has a label column which, if not void, will trigger a write of the current Line address into one of 15 bytes of Jump address memory. When a subsequent line command requires a jump, the label specified is the address of the Jump address. The Jump can be qualified by the result of a test at the current line.

Pattern Control and Timing block

What is seen at the DIO and DAC pins as a pattern executes is under the control of the Pattern Memory Address Counter.   Clocking or jamming the counter always causes a Read cycle.  So controlling when to clock or jam the counter controls the pattern. The Control Block does this task. It reads Line commands and the number of clocks to issue. It also controls start and stop and reports run status to the host.

DIO State Decoder and Test block

DIO data is not just force 1 or 0. To test and to interface to 3 state busses, the pins need further options:

Drive a One
Drive a Zero
High impedance
Test to be a One
Test to be a Zero
Output the System Clock

Miscellaneous

The entire design, excepting the DACs and nonvolatile memory, fits an FPGA, the Lattice MachX02 7000.  The design includes several housekeeping details such as :

  1. For parallel units running in synchronous operation, the FPGA provides two pins, a Start input and a Start output. One unit is chosen the master and its Start output would be wired to all slave Start inputs.
  2. Pause and then step or run again.
  3. Backup the control panel display with LEDs for standalone status display.
  4. Provide outputs that pulse the moment a test fails.

Mechanical Design

A Toolless plastic design was chosen for the enclosure which mates to a single PCB.


The final Validator hardware

The next step was to figure out the best way to get pattern data into a CSV file.

PATTERN TEMPLATE DESIGN

A pattern generator tool might sit in the toolbox for long periods until setup stimuli are needed. If specialized software is required to program the pattern, a refresher study of the manuals might have to proceed preparing patterns. Might there be an advantage if the pattern creation method used familiar software?

Since its inception, spreadsheet software has been adopted for a variety of chores, both business and personal. It could fit the label of “familiar software” and has advantages for creating patterns. The format could look like traditional ATE (Automated Test Equipment) with line by line time steps. Strong editing capabilities and auto indexing could make large patterns manageable. With an elapsed time column it would be possible to write equations as a function of time for the DAC voltages. For frequently used communication protocols, a couple of worksheets could make data handling simple, one for inputting data for transactions and another to automatically read the data and distribute to the right places for the download file. Choosing a fixed spreadsheet template should make it possible to enter pattern data immediately without refresher issues. A spreadsheet is easily saved as a CSV file.

Once settled on using the spreadsheet to input patterns, the next step was to assign the order of data in a template. The selected presentation was arbitrary and hopefully flows in a logical sequence.

FIGURE 2.  Pattern Entry Template

When the host software reads the CSV file, it will ignore any line without a Line Number in column A with the exception of Setup Data in row 7. It also ignores any data after the last column, which is column H for Setup Data and column X for Line Data. The ignored columns and rows can be used for annotation or housekeeping.

HOST SOFTWARE DESIGN

With hardware and pattern entry template defined, a host program is required to read the CSV file, format and deliver data to the USB sequencer, and receive back USB data to display status and results.

Visual C++ MFC was selected for this task.   A simple control panel with buttons and edit boxes was constructed using a Dialog Application:

                                        MFC Dialog Panel

Host software design tasks included:

  • Recognize and administrate the USB connection
  • Provide browsing for a CSV file to download
  • Error check the CSV file and provide intuitive messages to assist user debugging.
  • Send data from the selected download file to hardware by USB
  • Send codes to hardware when control button controls are pushed.
  • Periodically check for USB data coming from hardware and update the display in the edit boxes.


ADD A BREAKOUT BOARD

The DIO channels from the FPGA are 3.3V. To satisfy the “any digital voltage” objective, translators are required. A Breakout Board accessory is also needed to provide a connector option for interfacing DIO channels to a DUT. It was decided to combine the two requirements and design a Breakout Board with translators.

Each translated DIO channel should be bidirectional just like the non-translated FPGA DIO pins. One way to accomplish this is to use two 3.3V channels to make one translated channel. One 3.3V DIO channel is data (one, zero, or input) and the other 3.3V channel supplies direction. A TI SN74LVC1T45 bus transceiver was selected for the translators.

For translated patterns, a worksheet was made to look like the 16 channel template except there are only 8 DIO channels. The data from this worksheet is read by the cells of a standard 16 DIO template in a separate worksheet. The “reading” worksheet will become the CSV file. The “reading” DIO cells interpret the 8 translation DIO channel inputs to automatically create 8 pairs, direction and data. The user only has to remember to save the “reading” worksheet to CSV format for download.

The Breakout Board has duplicate connectors on each side of the board. One set is input to the translators. The other set is near the uncommitted area for wiring a mating connector to the DUT or perhaps to add interface electronics like protocol bus transceivers.

                                                        Breakout Board with Translators

 

EXAMPLE APPLICATION

To illustrate applying the Validator to a real world task, I wrote a step by step Example Application note, “Measure an ARINC 429 Receiver Threshold”. The DACs were used to generate a ramping amplitude differential voltage and the digital was used to do SPI communication. The target is a mixed signal IC, the HI-3598 which has an analog receiver whose threshold is measured.


Example Application Setup

 SPI routines followed by differential DAC waveforms

VALIDATOR 1 IS AVAILABLE

The finished product is available for purchase by a newly formed business called Sequim Tek located in, of course, Sequim, Washington.

Example Patterns are available for download including a pulse generator, a waveform generator, and an SPI communication example. They are meant to illustrate a few of the ways a pattern created by a spreadsheet can be customized.

About the Author
William Holt started designing CMOS ICs at Motorola SPD in 1970 after receiving a BSEE from the University of Utah. In 1976, he founded Holt IC in Southern California which provides standard IC products to the avionics and military markets.

Sponsored by: Sequim Tek