Cypress Semiconductor Corp. recently started volume shipments of microcontrollers containing its proprietary 40-nm Embedded Charge-Trap (eCT) Flash manufactured at United Microelectronics Corporation (UMC). The shipments are part of a multiple-year collaboration between Cypress and UMC to integrate Cypress’s flash technology with UMC’s 40-nm Low Power (40LP) logic process.
With a 0.053 µm2 cell size, the eCT Flash macro is capable of 8-ns random access and 30-μs word-programming speed, making it well suited for high-performance applications as well as stringent automotive reliability requirements. The eCT Flash macros are also available for licensing from Cypress.
Source: Cypress Semiconductor
ARM and United Microelectronics Corporation (UMC) recently announced the availability of a new ARM Artisan physical IP solution on 55 nm to accelerate the development of ARM processor-based embedded systems and Internet of Things (IoT) applications.
UMC’s 55-nm ultra-low-power process (55ULP) technology is emerging as an ideal solution for energy-efficient IoT applications. The new physical IP offering will enable silicon design teams to speed up and simplify the bring-up of ARM-based SoC designs for IoT and other embedded applications.
For many energy-constrained applications, maximizing battery life is critical to a successful design. The Artisan physical IP platform will enhance the ULP technology from UMC with the intent to maximize power efficiency and reduce leakage. Features such as thick gate oxide support and long, multi-channel library options give SoC designers multiple tools to help optimize IoT applications.
The Artisan libraries will support:
- The 0.9-V ultra-low voltage domain, thereby saving up to 44% dynamic power and 25% leakage power when compared to 1.2-V domain operation
- Multichannel libraries with multiple Vts to offer SoC designers leakage and performance options. Long channel libraries can be used to further reduce leakage by up to 80%. The Power Management Kit (PMK) enables both active and leakage power mitigation.
- Innovative thick gate oxide library will offer dramatically reduced leakage (350× lower than regular standard cells) for always ON cells. The ability of this library to interface with higher voltages (including battery voltages used in IoT devices) can also offer the advantage of negating the need for a voltage regulator.
- Next generation high-density memory compilers offer multiple integrated power modes to save state while minimizing standby leakage. Utilizing these modes will allow SoC designers to realize up to 95% lower leakage when compared to regular standby.
The UMC-based physical IP for 55ULP is available immediately via ARM’s DesignStart portal.