Issue 278: EQ Answers

Problem 1—Tom, an FPGA designer, is helping out on a system that handles standard-definition digital video at 27 MHz and stores it into an SDRAM that runs at 200 MHz. He discovered the following logic in the FPGA (see Figure 1).

Let’s see if we can work out what it does. To start with, what is the output of the XOR gate in?

Answer 1—When the 27-MHz clock goes from low to high, the first flip-flop changes state. Let’s say that its output goes from low to high as well. Then, when the clock goes from high to low, the second flip-flop’s output will become the same as the first.

On the clock’s next rising edge, the first flip-flop will change again, this time from high to low. And on the next falling edge, the second one will follow suit.

Putting it another way, following each rising edge of the clock, the two flip-flops are different. Following each falling edge, they’re the same. Since we’re feeding them into an XOR gate, the gate’s output will be high following the clock’s rising edge and low following the falling edge. In other words, the XOR gate’s is a replica of the clock signal itself!

Problem 2—Why is this necessary?

Answer 2—In many FPGA architectures, clock signals are automatically assigned to special clock routing resources, which are different from—and kept separate from—the routing resources used for “ordinary” signals. The tools actually discourage (or even prevent) you from using a clock as an input to a gate or to any input of a flip-flop other than the clock input.

Therefore, when you need to pass a clock into another timing domain as a signal, it becomes necessary to generate an ordinary signal that is a replica of the clock. This is one way to accomplish that.

Problem 3—What is the AND gate’s output?

Answer 3—The three flip-flops in the 200-MHz domain have a delayed versions of the (replica) 27-MHz clock signal. The first two function as a conventional synchronizer to minimize the effects of metastability. The third one, along with the AND gate, functions as an edge detector, generating a one-clock pulse in the 200-MHz clock domain following each rising edge of the 27-MHz clock. This pulse might be used, for example, to initiate a write request in the SDRAM for each video data word.

Problem 4—Tom decided to verify the circuit’s operation in his logic simulator, but immediately ran into a problem. What was the problem and what could be added to the circuit to make simulation possible?

Answer 4—There is a subtle problem here for a simulator: All of the flip-flops start out in the “unknown” state. Feeding that back (inverted) to the first flip-flop leaves it in an unknown state. The entire simulation will never get out of the unknown state, even though we can reason that it doesn’t matter which actual state the first flip-flop starts out in. The XOR gate’s output will be known after one full clock cycle. To fix this, it is necessary to explicitly reset the first flip-flop at the beginning of the simulation, then the rest of the circuit will simulate normally.

Issue 276: EQ Answers

Problem 1
Suppose you have an ordinary switch mode buck regulator. The input voltage is 100 V, the switch’s duty cycle is exactly 50%, and you measure the output voltage as 70 V. Is this converter operating in continuous conduction mode or discontinuous conduction mode? How can you tell?

Answer 1
If a switch mode buck converter is operating in continuous conduction mode, then the output voltage is the fraction of the input voltage as defined by the duty cycle. 100 V × 0.5 would equal 50 V. Therefore, this converter is operating in discontinuous conduction mode.

Note that continuous conduction mode includes the case in which synchronous (active) rectification is being used and the current through the coil is allowed to reverse direction when the output is lightly loaded. The output voltage in relation to the input voltage will still be defined by the switch duty cycle.

Therefore, we also know that the regulator in question is not using synchronous rectification, but rather is using a diode instead.

Problem 2
Since a diode can be placed in a High-Impedance state (reverse-biased) or a Low-Impedance state (forward-biased), they are sometimes used to switch AC signals, including audio and RF. What determines the magnitude of a signal that a diode can switch?

Answer 2
When diodes are used for signal switching, there are two considerations with regard to the magnitude of the signal relative to the DC control signal:

  • In the Blocking state, the reverse bias voltage must be greater than the peak signal voltage to prevent signal leakage. Also, a high-bias voltage reduces the parasitic capacitance through the diode. PIN diodes are often used for RF switching because of their ultra-low capacitance.
  • In the On state, the forward DC control current through diode must be greater than the peak AC signal current, and it must be large enough so that the current doesn’t approach the diode curve’s “knee” too closely, introducing distortion.

Obviously, the diode needs to be rated for both the peak reverse voltage and the peak forward current created by the combination of the control signal and the application signal.

Problem 3
What common function does the following truth table represent?

0 0 0 ? 0 0 0
0 0 1 ? 0 0 1
0 1 0 ? 0 1 0
0 1 1 ? 0 0 1
1 0 0 ? 1 0 0
1 0 1 ? 0 0 1
1 1 0 ? 0 1 0
1 1 1 ? 0 0 1

Answer 3
The truth table implements a form of priority encoder:

Z is set if C is set, otherwise
Y is set if B is set, otherwise
X is set if A is set

In other words, C has the highest priority and A has the lowest. However, unlike conventional priority encoders that produce a binary output, this one produces a “one hot” encoding.

Problem 4
Write the equations for the logic that would implement the table.

Answer 4
The logic is quite straightforward:

Z = C
Y = B & !C
X = A & !B & !C

Issue 274: EQ Answers

The answers to the Circuit Cellar 274 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—What is wrong with the name “programmable unijunction transistor?”

Answer 1—Unlike the original unijunction transistor—which really does have just a single junction—the programmable unijunction transistor (PUT) is actually a four-layer device that has three junctions, much like a silicon-controlled rectifier (SCR).


Problem 2—Given a baseband channel with 3-kHz bandwidth and a 40-dB signal-to-noise ratio (SNR), what is the theoretical capacity of this channel in bits per second?

Answer 2—The impulse response of an ideal channel with exactly 3 kHz of bandwidth is a sinc (i.e., sin(x)/x) pulse in the time domain that has nulls that are 1/6,000 s apart. This means you could send a series of impulses through this channel at a 6,000 pulses per second rate. And, if you sampled at exactly the correct instants on the receiving end, you could recover the amplitudes of each of those pulses with no interference from the other pulses on either side of it.

However, a 40-dB signal-to-noise ratio implies that the noise power is 1/10,000 of the maximum signal power. In terms of distinguishing voltage or current levels, this means you can send at most sqrt(10,000) = 100 distinct levels through the channel before they start to overlap, making it impossible to separate one from another at the receiving end.

100 levels translates to log2100 = 6.64 binary bits of information. This means the total channel capacity is 3,9840 bits/s (i.e., 6,000 pulses/s × 6.64 bits/pulse).

This is the basis for the Shannon-Hartley channel capacity theorem.


Problem 3—In general, is it possible to determine whether a system is linear and time-invariant (LTI) by simply examining its input and output signals?

Answer 3—In general, given an input signal and an output signal, you might be able to definitively state that the system is not linear and time-invariant (LTI), but you’ll never be able to definitively state that it is, only that it might be.

The general technique is to use information in the input signal to see whether the output signal can be composed from the input features. Input signals (e.g., impulses and steps) are easist to analyze, but other signals can also be analyzed.


Problem 4—One particular system has this input signal:

Figure 1

The output is given by:

Figure 2

Is this system LTI?

Answer 4—In this example, the input is a rectangular pulse that can be analyzed as the superposition of two step functions that are separated in time, one positive-going and the other negative-going. This makes the analysis easy, since you can see the initial response to the first step function then determine whether the response following the second step is a linear combination of two copies of the first part of the response.

In this case, the response to the first step function at t = 0 is that the output starts rising linearly, also at t = 0. The second (negative) input step function occurs at t = 0.5, and if the system is LTI, you would expect the output to also change what it’s doing at that time. In fact, you would expect the output to level off at whatever value it had reached at that time, because the LTI response to the second step should be a negative-going linear ramp, which, when added to the original response, should cancel out.

However, this is not the output signal received, so this system is definitely not LTI.

Issue 272: EQ Answers

The answers to the Circuit Cellar 272 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—Why does the power dissipation of a Darlington transistor tend to be higher than that of a single bipolar transistor in switching applications?

Answer 1—In switching applications, a single transistor can saturate, resulting in a low VCE of 0.3 to 0.4 V. However, in a Darlington pair, the output transistor is prevented from saturating by the negative feedback provided by the driver transistor. If the collector voltage drops below the sum of the VBE of the output transistor (about 0.7 V) and the VCE(sat) of the driver transistor (about 0.3 V), the drive current to the output transistor is reduced, preventing it from going into saturation itself. Therefore, the effective VCE(sat) of the Darlington pair is 1 V or more, resulting in much higher dissipation at a given current level.

Problem 2—Suppose you have some 3-bit data, say, grayscale values for which 000 = black and 111 = white. You have a display device that takes 8-bit data, and you want to extend the bit width of your data to match.

If you just pad the data with zeros, you get the value 11100000 for white, which is not full white for the 8-bit display—that would be 11111111. What can you do?

Answer 2—One clever trick is to repeat the bits you have as many times as necessary to fill the output field width. For example, if the 3-bit input value is ABC, the output value would be ABCABCAB. This produces the following mapping, which interpolates nicely between full black and full white (see Table 1). Note that this mapping preserves the original bits; if you want to go back to the 3-bit representation, just take the MSBs and you have the original data.

3-bit INPUT 8-bit OUTPUT
000 00000000
001 00100100
010 01001001
011 01101101
100 10010010
101 10110110
110 11011011
111 11111111

Problem 3—Can an induction motor (e.g., squirrel-cage type) be used as a generator?

Answer 3—Believe it or not, yes it can.

An induction motor has no electrical connections to the rotor; instead, a magnetic field is induced into the rotor by the stator. The motor runs slightly slower than “synchronous” speed—typically 1725 or 3450 rpm when on 60 Hz power.

If the motor is provided with a capacitive load, is driven at slightly higher than synchronous speed (1875 or 3750 rpm), and has enough residual magnetism in the rotor to get itself going, it will generate power up to approximately its rating as a motor. The reactive current of the load capacitor keeps the rotor energized in much the same way as when it is operating as a motor.

See for additional details.

Problem 4—In Figure 1, why does this reconstruction of a 20-kHz sinewave sampled at 44.1 kHz show ripple in its amplitude?

Answer 4—The actual sampled data, represented by the square dots in the diagram, contains equal levels of Fsignal (the sine wave) and Fsample-Fsignal (one of the aliases of the sinewave). Any reconstruction filter is going to have difficulty passing the one and eliminating the other, so you inevitably get some of the alias signal, which, when added to the desired signal, produces the “modulation” you see.

In the case of a software display of a waveform on a computer screen (e.g., such as you might see in software used to edit audio recordings), they’re probably using an FIR low-pass filter (sin(x)/x coefficients) windowed to some finite length. A shorter window gives faster drawing times, so they’re making a tradeoff between visual fidelity and interactive performance. The windowing makes the filter somewhat less than brick-wall, so you get the leakage of the alias and the modulation.

In the case of a real audio D/A converter, even with oversampling you can’t get perfect stopband attenuation (and you must always do at least some of the filtering in the analog domain), so once again you see the leakage and modulation.

In this example, Fsignal = 0.9×Fnyquist, so Falias = 1.1×Fnyquist and Falias/Fsignal = 1.22. To eliminate the visible artifacts, the reconstruction filter would need to have a slope of about 60dB over this frequency span, or about 200 dB/octave.

Issue 270: EQ Answers

The answers to the Circuit Cellar 270 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1: Given a microprocessor that has hardware support for just one level of priority for interrupts, is it possible to implement multiple priorities in software? If so, what are the prerequisites that are required?

Answer 1: Yes, given a few basic capabilities, it is possible to implement multiple levels of interrupt priority in software. The basic requirements are that it must be possible to reenable interrupts from within an interrupt service routine (ISR) and that the different interrupt sources can be individually masked.

Question 2: What is the basic scheme for implementing software interrupt priorities?

Answer 2: In normal operation, all the interrupt sources are enabled, along with the processor’s global-interrupt mask.

When an interrupt occurs, the global interrupt mask is disabled and the “master” ISR is entered. This code must (quickly) determine which interrupt occurred, disable that interrupt and all lower-priority interrupts at their sources, then reenable the global-interrupt mask before jumping to the ISR for that interrupt. This can often be facilitated by precomputing a table of interrupt masks for each priority level.

Question 3: What are some of the problems associated with software interrupt priorities?

Answer 3: For one thing, the start-up latency of all the ISRs is increased by the time spent in the “master” ISR. This can be a problem in time-critical systems. This scheme enables interrupts to be nested, so the stack must be large enough to handle the worst-case nesting of ISRs, on top of the worst-case nesting of non-interrupt subroutine calls.

Finally, it is very tricky to do this in anything other than Assembly language. If you want to use a high-level language, you’ll need to be intimately familiar with the language’s run-time library and how it handles interrupts and reentrancy, in general.

Answer 4: Yes, on most such processors, you can execute a subroutine call to a “return from interrupt” instruction while still in the master ISR, which will then return to the master ISR, but with interrupts enabled.

Check to see whether the “return from interrupt” affects any other processor state (e.g., popping a status word from the stack) and prepare the stack accordingly.

Also, beware that another interrupt could occur immediately thereafter, and make sure the master ISR is reentrant beyond that point.


Contributed by David Tweed