Technology and Test Solutions for 5G

Next-Gen Communications

As carriers worldwide prepare for 5G communications, chip suppliers and test equipment vendors are evolving their products to meet the challenges of the 5G era.

By Jeff Child, Editor-in-Chief

The technologies that are enabling 5G communications are creating new challenges for embedded system developers. Faster mobile broadband data rates, massive amounts of machine-to-machine network interfacing and daunting low latency constraints all add to the complexity of 5G system design. Feeding those needs, chip vendors over the past 12 months have been releasing building blocks like modem chips and wideband mixers supporting 5G. And test equipment vendors are keeping pace with test gear designed to work with 5G technology.

With standards expected to reach finalization around 2020, 5G isn’t here yet, But efforts worldwide are laying the groundwork to deploy it. For its part, the Global mobile Suppliers Association (GSA) released a report in October 2017 entitled “Evolution from LTE to 5G.” According to the report, there is a frenzy of testing of 5G technology and concepts worldwide. The GSA has identified 103 operators in 49 countries that are investing in 5G technology in the form of demos, lab trials or field tests that are either under way or planned. Operators are sharing their intentions in terms of launch timetables for 5G, or prestandards 5G. The earliest launch dates currently planned are by operators in Italy and the US. Those early launches are necessarily limited in scope to either specific applications, or in limited geographic areas where they will function as extended commercial trials. Figure 1 shows the countries and the current planned dates for the earliest 5G launches in those countries.

FIGURE 1
Here is a map of pre-standards and standards-based 5G network plans announced. It shows the countries and current planned dates for the earliest 5G launches in those countries. (Source: Global mobile Suppliers Association (GSA)).

THE BIG PLAYERS

Intel and Qualcomm have been the big players to watch for 5G enabling technologies. In October 2017, Qualcomm Technologies, a subsidiary of Qualcomm, hit a significant milestone successfully achieving a 5G data connection on a 5G modem chipset for mobile devices. The Qualcomm Snapdragon X50 5G modem chipset achieved speeds and a data connection in the 28 GHz mmWave radio frequency band. The solution is expected to accelerate the delivery of 5G new radio (5G NR) enabled mobile devices to consumers. Along with the chip set demo Qualcomm Technologies previewed its first 5G smartphone reference design for the testing and optimization of 5G technology within the power and form-factor constraints of a smartphone.

The 5G data connection demonstration showed the chip set achieving Gigabit/s download speeds, using several 100 MHz 5G carriers and demonstrated a data connection in the 28 GHz millimeter wave (mmWave) spectrum. In addition to the Snapdragon X50 5G modem chipset, the demonstration also used the SDR051 mmWave RF transceiver IC. The demonstration made use of Keysight Technologies’ new 5G Protocol R&D Toolset and UXM 5G Wireless Test Platform. Qualcomm Technologies was the first company to announce a 5G modem chipset in 2016. The Snapdragon X50 5G NR modem family is expected to support commercial launches of 5G smartphones and networks in the first half of 2019. …

Read the full article in the January 330 issue of Circuit Cellar

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Note: We’ve made the October 2017 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

The Future of Test-First Embedded Software

The term “test-first” software development comes from the original days of extreme programming (XP). In Kent Beck’s 1999 book, Extreme Programming Explained: Embrace Change (Addison-Wesley), his direction is to create an automated test before making any changes to the code.

Nowadays, test-first development usually means test-driven development (TDD): a well-defined, continuous feedback cycle of code, test, and refactor. You write a test, write some code to make it pass, make improvements, and then repeat. Automation is key though, so you can run the tests easily at any time.

TDD is well regarded as a useful software development technique. The proponents of TDD (including myself) like the way in which the code incrementally evolves from the interface as well as the comprehensive test suite that is created. The test suite is the safety net that allows the code to be refactored freely, without worry of breaking anything. It’s a powerful tool in the battle against code rot.

To date, TDD has had greater adoption in web and application development than with embedded software. Recent advances in unit test tools however are set to make TDD more accessible for embedded development.

In 2011 James Grenning published his book, Test Driven Development for Embedded C (Pragmatic Bookshelf). Six years later, this is still the authoritative reference for embedded test-first development and the entry point to TDD for many embedded software developers. It explains how TDD works in detail for an unfamiliar audience and addresses many of the traditional concerns, like how will this work with custom hardware. Today, the book is still completely relevant, but when it was published, the state-of-the art tools were simple unit test and mocking frameworks. These frameworks require a lot of boilerplate code to run tests, and any mock objects need to be created manually.

In the rest of the software world though, unit test tools are significantly more mature. In most other languages used for web and application development, it’s easy to create and run many unit tests, as well as to create mock objects automatically.
Since 2011, the current state of TDD tools has advanced considerably with the development of the open-source tool Ceedling. It automates running of unit tests and generation of mock objects in C applications, making it a lot easier to do TDD. Today, if you want to test-drive embedded software in C, you don’t need to roll-your-own test build system or mocks.

With better tools making unit testing easier, I suspect that in the future test-first development will be more widely adopted by embedded software developers. While previously relegated to the few early adopters willing to put in the effort, with tools lowering the barrier to entry it will be easier for everyone to do TDD.
Besides the tools to make TDD easier, another driving force behind greater adoption of test-first practices will be the simple need to produce better-quality embedded software. As embedded software continues its infiltration into all kinds of devices that run our lives, we’ll need to be able to deliver software that is more reliable and more secure.

Currently, unit tests for embedded software are most popular in regulated industries—like medical or aviation—where the regulators essentially force you to have unit tests. This is one part of a strategy to prevent you from hurting or killing people with your code. The rest of the “unregulated” embedded software world should take note of this approach.

With the rise of the Internet of things (IoT), our society is increasingly dependent on embedded devices connected to the Internet. In the future, the reliability and security of the software that runs these devices is only going to become more critical. There may not be a compelling business case for it now, but customers—and perhaps new regulators—are going to increasingly demand it. Test-first software can be one strategy to help us deal with this challenge.


This article appears in Circuit Cellar 318.


Matt Chernosky wants to help you build better embedded software—test-first with TDD. With years of experience in the automotive, industrial, and medical device fields, he’s excited about improving embedded software development. Learn more from Matt about getting started with embedded TDD at electronvector.com.

eSOL RTOS & Debugger Support for Software Development

Imperas Software recently announced its support for eSOL’s eMCOS RTOS and eBinder debugger. The partnership is intended to accelerate embedded software development, debugging, and testing.

The Imperas Extendable Platform Kit (EPK) features a Renesas RH850F1H device and it runs the eSOL eMCOS real time operating system. Imperas simulators can use the debugger from the eSOL IDE, eBinder, for efficient software debugging and testing.

Source: eSOL

New RF Signal Generator

RIGOL Technologies recently expanded its portfolio of RF Test solutions with the launch of the DSG800 Series RF Signal Generator. The series—which is targeted at engineers implementing Bluetooth, Wi-Fi, and other RF interfaces in embedded systems—covers output frequencies from 9 kHz to 3 GHz. It provides maximum output power up to 20 dBm and low SSB phase noise of –105 dBc/Hz, amplitude accuracy of ±0.5 dB, and frequency resolution 0.01 Hz at any frequency. An oven-controlled crystal oscillator timebase provides less than 5 ppb temperature stability and less than 30 ppb/year aging stability.DSG800 Rigol

The DSG800 RF signal generators provide:

  • Conventional sweep functions (step, list, logarithmic, and linear)
  • Analog modulation functions including amplitude modulation (AM), frequency modulation (FM), phase modulation (ΦM), and pulse modulation
  • An optional pulse train generation capability for translating serial data onto an RF link

    There are two models in the DSG800 series. THe DSG815 (9 kHz to 1.5 GHz) costs $1,999. The DSG830 (9 kHz to 3 GHz) costs $3,599.

Source: RIGOL Technologies

Issue 286: EQ Answers

Question 1—A divider is a logic module that takes two binary numbers and produces their numerical quotient (and optionally, the remainder). The basic structure is a series of subtractions and multiplexers, where the multiplexer uses the result of the subtraciton to select the value that gets passed to the next step. The quotient is formed from the bits used to control the multiplexers, and the remainder is the result of the last subtraction.

If it is implemented purely combinatorially, then the critical path through all of this logic is quite long (even with carry-lookahead in the subtractors) and the clock cycle must be very slow. What could be done to shorten the clock period without losing the ability to get a result on every clock?

Answer 1—Pretty much any large chunk of combinatorial logic can be pipelined in order to reduce the clock period. This allows it to produce more results in a given amount of time, at the expense of increasing the latency for any particular result.

Divider logic is very easy to pipeline, and the number of pipeline stages you can use is fairly arbitrary. You could insert a pipeline register after each subtract-mux pair, or you might choose to do two or more subtract-mux stages per pipeline register You could even go so far as to pipeline the subtracts and the muxes separately (or even pipeline *within* each subtract) in order to get the fastest possible clock speed, but this would be rather extreme.

The more pipeline registers you use, the shorter the critical path (and the clock period) can be, but you use more resources (the registers). Also, the overall latency goes up, since you need to account for the setup and propagation times of the pipeline registers in the clock period (in addition to the subtract-mux logic delays). This gets multiplied by the number of pipeline stages in order to compute the total latency.

Question 2—On the other hand, what could be done to reduce the amount of logic required for the divider, giving up the ability to have a result on every clock?

 

Answer 2—If you don’t need the level of performance provided by a pipelined divider, you can computes the quotient serially, one bit at a time. You would just need one subtractor and one multiplexer, along with registers to hold the input values, quotient bits and the intermediate result.

You could potentially compute more than one bit per clock period using additional subtract-mux stages. This gives you the flexibility to trade off space and time as needed for a particular application.

Question 3—An engineer wanted to build an 8-MHz filter that had a very narrow bandwidth, so he used a crystal lattice filter like this:

EQ-fig1-CC287-June14

However, when he built and tested his filter, he discovered that while it worked fine around 8 MHz, the attenuation at very high frequencies (e.g., >80 MHz) was very much reduced. What caused this?

Answer 3—The equivalent circuit for a quartz crystal is something like this:EQ-fig2-CC287-June14

The components across the bottom represent the mechanical resonance of the crystal itself, while the capacitor at the top represents the capacitance of the electrodes and holder. Typical values are:

  • Cser: 10s of fF (yes, femtofarads, 10-15F)
  • L: 10s of mH
  • R: 10s of ohms
  • Cpar: 10s of pF

The crystal has a series-resonant frequency based on just Cser and L. It has a relatively low impedance (basically just R) at this frequency.

It also has a parallel-resonant (sometimes called “antiresonant”) frequency when you consider the entire loop, including Cpar. Since Cser and Cpar are essentially in series, together they have a slightly lower capacitance than Cser alone, so the parallel-resonant frequency is slightly higher. The crystal’s impedance is very high at this frequency.

But at frequencies much higher than either of the resonant frequencies, you can see that the impedance of Cparalone dominates, and this just keeps decreasing with increasing frequency. This reduces the crystal lattice filter to a simple capacitive divider, which passes high freqeuncies with little attenuation.

Question 4—Suppose you know that a nominal 10.000 MHz crystal has a series-resonant frequency of 9.996490 MHz and a parallel-resonant frequency of 10.017730 MHz. You also know that its equivalent series capacitance is 27.1 fF. How can you calculate the value of its parallel capacitance?

Answer 4—First, calculate the crystal’s equivalent inductance, based on the series-resonant frequency:EQ-equation1-CC287-June14

Next, calculate the capacitance required to resonate with that inductance at the parallel-resonant frequency:EQ-equation2-CC287-June14

Finally, calculate the value of Cpar required to give that value of capacitance when in series with Cser:EQ-equation3-CC287-June14

Note that all three equations can be combined into one, and this reduces to:EQ-equation4-CC287-June14

Build an Adequate Test Bench (EE Tip #127)

It’s in our makeup as engineers that we want to test our newly received boards as soon as possible. We just can’t wait to connect them to a power supply and then use our test bench equipment (e.g., generators, oscilloscopes, switches or LEDs, and so on) for simulation.

Circuit Cellar columnist Robert Lacoste's workspace in Chaville, France.

Circuit Cellar columnist Robert Lacoste’s clean, orderly workspace in Chaville, France.

But due to our haste, the result is usually a PCB under test lying on a crowded workbench in the middle of a mesh of test cables, alligator clamps, prototyping boards, and other probes. Experience shows that the probability of a short circuit or mismatched connection is high during this phase of engineering excitement.

Test Board

Rather than requiring a mesh of test wires, it is often wise to develop a small test PCB that will drastically simplify the test phase. Here the ancillary board provided a clean way to connect a Microchip Technology ICD3 debugger, a JTAG emulator, a debug analyzer, and a power supply input.

Take your time: prepare a real test bench to which you can connect your board. It could be as simple as a clean desk with properly labeled wires, but you might also need to anticipate the design of a test PCB in order to simplify the cabling.—Robert Lacoste, “Mixed-Signal Designs,” CC25:25th Anniversary Issue, 2013. 

 

Issue 284: EQ Answers

PROBLEM 1
Can you name all of the signals in the original 25-pin RS-232 connector?

ANSWER 1
Pins 9, 10, 11, 18, and 25 are unassigned/reserved. The rest are:

Pin Abbreviation Source Description
1 PG Protective ground
2 TD DTE Transmitted data
3 RD DCE Received data
4 RTS DTE Request to send
5 CTS DCE Clear to send
6 DSR DCE Data Set Ready
7 SG Signal ground
8 CD DCE Carrier detect
12 SCD DCE Secondary carrier detect
13 SCTS DCE Secondary clear to send
14 STD DTE Secondary transmitted data
15 TC DCE Transmitter clock
16 SRD DCE Secondary received data
17 RC DCE Receiver clock
19 SRTS DTE Secondary request to send
20 DTR DTE Data terminal ready
21 SQ DCE Signal quality
22 RI DCE Ring indicator
23 DTE Data rate selector
24 ETC DTE External transmitter clock

 

PROBLEM 2
What is the key difference between a Moore state machine and a Mealy state machine?

ANSWER 2
The key difference between Moore and Mealy is that in a Moore state machine, the outputs depend only on the current state, while in a Mealy state machine, the outputs can also be affected directly by the inputs.

 

PROBLEM 3
What are some practical reasons you might choose one state machine over the other?

ANSWER 3
In practice, the difference between Moore and Mealy in most situations is not very important. However, when you’re trying to optimize the design in certain ways, it sometimes is.

Generally speaking, a Mealy machine can have fewer state variables than the corresponding Moore machine, which will save physical resources on a chip. This can be important in low-power designs.

On the other hand, a Moore machine will typically have shorter logic paths between flip-flops (total combinatorial gate delays), which will enable it to run at a higher clock speed than the corresponding Mealy machine.

 

PROBLEM 4
What is the key feature that distinguishes a DSP from any other general-purpose CPU?

ANSWER 4
Usually, the key distinguishing feature of a DSP when compared with a general-purpose CPU is that the DSP can execute certain signal-processing operations with few, if any, CPU cycles wasted on instructions that do not compute results.

One of the most basic operations in many key DSP algorithms is the MAC (multiply-accumulate) operation, which is the fundamental step used in matrix dot and cross products, FIR and IIR filters, and fast Fourier transforms (FFTs). A DSP will typically have a register and/or memory organization and a data path that enables it to do at least 64 MAC operations (and often many more) on unique data pairs in a row without any clocks wasted on loop overhead or data movement. General-purpose CPUs do not generally have enough registers to accomplish this without using additional instructions to move data between registers and memory.

Issue 282: EQ Answers

PROBLEM 1
Construct an electrical circuit to find the values of Xa, Xb, and Xc in this system of equations:

21Xa – 10Xb – 10Xc = 1
–10Xa + 22Xb – 10Xc = –2
–10Xa – 10Xb + 20Xc = 10

Your circuit should include only the following elements:

one 1-Ω resistor
one 2-Ω resistor
three 10-Ω resistors
three ideal constant voltage sources
three ideal ammeters

The circuit should be designed so that each ammeter displays one of the values Xa, Xb, or Xc. Given that the Xa, Xb, and Xc values represent currents, what kind of circuit analysis yields equations in this form?

ANSWER 1
You get equations in this form when you do mesh analysis of a circuit. Each equation represents the sum of the voltages around one loop in the mesh.

PROBLEM 2
What do the coefficients on the left side of the equations represent? What about the constants on the right side?

ANSWER 2
The coefficients on the left side of each equation represent resistances. Resistance multiplied by current (the unknown Xa, Xb, and Xc values) yields voltage.
The “bare” numbers on the right side of each equation represent voltages directly (i.e., independent voltage sources).

PROBLEM 3
What is the numerical solution for the equations?

ANSWER 3
To solve the equations directly, start by solving the third equation for Xc and substituting it into the other two equations:

Xc = 1/2 Xa + 1/2 Xb + 1/2

21Xa – 10Xb – 5Xa – 5Xb – 5 = 1
–10Xa + 22Xb – 5Xa – 5Xb – 5 = –2

16Xa – 15Xb = 6
–15Xa + 17Xb = 3

Solve for Xa by multiplying the first equation by 17 and the second equation by 15 and then adding them:

272Xa – 255Xb = 102
–225Xa + 255Xb = 45

47Xa = 147 → Xa = 147/47

Solve for Xb by multiplying the first equation by 15 and the second equation by 16 and then adding them:

240Xa – 225Xb = 90
–240Xa + 272Xb = 48

47Xb = 138 → Xb = 138/47

Finally, substitute those two results into the equation for Xc:

Xc = 147/94 + 138/94 + 47/94 = 332/94 = 166/47

PROBLEM 4
Finally, what is the actual circuit? Draw a diagram of the circuit and indicate the required value of each voltage source.

ANSWER 4
The circuit is a mesh comprising three loops, each with a voltage source. The common elements of the three loops are the three 10-Ω resistors, connected in a Y configuration (see the figure below).

cc281_eq_fig1The values of the voltage sources in each loop are given directly by the equations, as shown. To verify the numeric solution calculated previously, you can calculate all of the node voltages around the outer loop, plus the voltage at the center of the Y, and ensure they’re self-consistent.

We’ll start by naming Va as ground, or 0 V:

Vb = Va + 2 V = 2 V

Vc = Vb + 2 Ω × Xb = 2V + 2 Ω × 138/47 A = 370/47 V = 7.87234 V

Vd = Vc + 1 Ω × Xa = 370/47 V + 1 Ω × 147/47A = 517/47 V = 11.000 V

Ve = Vd – 1 V = 11.000 V – 1.000 V = 10.000 V

Va = Ve – 10 V = 0 V

which is where we started.

The center node, Vf, should be at the average of the three voltages Va, Vc, and Ve:

0 V + 370/47 V + 10 V/3 = 840/141 V = 5.95745 V

We should also be able to get this value by calculating the voltage drops across each of the three 10-Ω resistors:

Va + (Xc – Xb) × 10 Ω = 0 V + (166 – 138)/47A × 10 Ω = 280/47 V = 5.95745 V

Vc + (Xb – Xa) × 10 Ω = 370/47V + (138-147)/47A × 10 Ω = 280/47 V = 5.95745 V

Ve + (Xa – Xc) × 10 Ω = 10 V + (147-166)/47 A × 10 Ω = 280/47 V = 5.95745 V

Issue 280: EQ Answers

PROBLEM 1
What is the key difference between the following two C functions?

#define VOLTS_FULL_SCALE 5.000
#define KPA_PER_VOLT 100.0
#define KPA_THRESHOLD 200.0

/* adc_reading is a value between 0 and 1
 */
bool test_pressure (float adc_reading)
{
  float voltage = adc_reading * VOLTS_FULL_SCALE;
  float pressure = voltage * KPA_PER_VOLT;

  return pressure > KPA_THRESHOLD;
}

bool test_pressure2 (float adc_reading)
{
  float voltage_threshold = KPA_THRESHOLD / KPA_PER_VOLT;
  float adc_threshold = voltage_threshold / VOLTS_FULL_SCALE;

  return adc_reading > adc_threshold;
}

ANSWER 1
The first function, test_pressure(), converts the ADC reading to engineering units before making the threshold comparison. This is a direct, obvious way to implement such a function.

The second function, test_pressure2(), converts the threshold value to an equivalent ADC reading, so that the two can be compared directly.

The key difference is in performance. The first function requires that arithmetic be done on each reading before making the comparison. However, the calculations in the second function can all be performed at compile time, which means that the only run-time operation is the comparison itself.

PROBLEM 2
How many NAND gates would it take to implement the following translation table? There are five inputs and eight outputs. You may consider an inverter to be a one-input NAND gate.

Inputs Outputs
A B C D E   F G H I J K L M
1 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 1 1 0 0 0 0 0 0 1 1
0 0 1 1 1 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 0 0 1 1
0 0 0 0 1 1 0 0 0 1 1 1 1

 

ANSWER 2
First of all, note that there are really only four inputs and three unique outputs for this function, since input E is always 1 and outputs GHI are always 0. The only real outputs are F, plus the groups JK and LM.

Since the other 27 input combinations haven’t been specified, we can take the output values associated with all of them as “don’t care.”

The output F is simply the inversion of input C.

The output JK is high only when A is high or D is low.

The output LM is high except when B is low and C is high.

Therefore, the entire function can be realized with a total of five gates:

eq0641_fig1

PROBLEM 3
Quick history quiz: Who were the three companies who collaborated to create the initial standard for the Ethernet LAN?

ANSWER 3
The original 10-Mbps Ethernet standard was jointly developed by Digital Equipment Corp. (DEC), Intel, and Xerox. It was released in November 1980, and was commonly referred to as “DIX Ethernet.”

PROBLEM 4
What was the name of the wireless network protocol on which Ethernet was based? Where was it developed?

ANSWER 4
The multiple access with collision detection protocol that Ethernet uses was based on a radio protocol developed at the University of Hawaii. It was known as the “ALOHA protocol.”

Issue 278: EQ Answers

Problem 1—Tom, an FPGA designer, is helping out on a system that handles standard-definition digital video at 27 MHz and stores it into an SDRAM that runs at 200 MHz. He discovered the following logic in the FPGA (see Figure 1).

Let’s see if we can work out what it does. To start with, what is the output of the XOR gate in?

Answer 1—When the 27-MHz clock goes from low to high, the first flip-flop changes state. Let’s say that its output goes from low to high as well. Then, when the clock goes from high to low, the second flip-flop’s output will become the same as the first.

On the clock’s next rising edge, the first flip-flop will change again, this time from high to low. And on the next falling edge, the second one will follow suit.

Putting it another way, following each rising edge of the clock, the two flip-flops are different. Following each falling edge, they’re the same. Since we’re feeding them into an XOR gate, the gate’s output will be high following the clock’s rising edge and low following the falling edge. In other words, the XOR gate’s is a replica of the clock signal itself!

Problem 2—Why is this necessary?

Answer 2—In many FPGA architectures, clock signals are automatically assigned to special clock routing resources, which are different from—and kept separate from—the routing resources used for “ordinary” signals. The tools actually discourage (or even prevent) you from using a clock as an input to a gate or to any input of a flip-flop other than the clock input.

Therefore, when you need to pass a clock into another timing domain as a signal, it becomes necessary to generate an ordinary signal that is a replica of the clock. This is one way to accomplish that.

Problem 3—What is the AND gate’s output?

Answer 3—The three flip-flops in the 200-MHz domain have a delayed versions of the (replica) 27-MHz clock signal. The first two function as a conventional synchronizer to minimize the effects of metastability. The third one, along with the AND gate, functions as an edge detector, generating a one-clock pulse in the 200-MHz clock domain following each rising edge of the 27-MHz clock. This pulse might be used, for example, to initiate a write request in the SDRAM for each video data word.

Problem 4—Tom decided to verify the circuit’s operation in his logic simulator, but immediately ran into a problem. What was the problem and what could be added to the circuit to make simulation possible?

Answer 4—There is a subtle problem here for a simulator: All of the flip-flops start out in the “unknown” state. Feeding that back (inverted) to the first flip-flop leaves it in an unknown state. The entire simulation will never get out of the unknown state, even though we can reason that it doesn’t matter which actual state the first flip-flop starts out in. The XOR gate’s output will be known after one full clock cycle. To fix this, it is necessary to explicitly reset the first flip-flop at the beginning of the simulation, then the rest of the circuit will simulate normally.

Issue 276: EQ Answers

Problem 1
Suppose you have an ordinary switch mode buck regulator. The input voltage is 100 V, the switch’s duty cycle is exactly 50%, and you measure the output voltage as 70 V. Is this converter operating in continuous conduction mode or discontinuous conduction mode? How can you tell?

Answer 1
If a switch mode buck converter is operating in continuous conduction mode, then the output voltage is the fraction of the input voltage as defined by the duty cycle. 100 V × 0.5 would equal 50 V. Therefore, this converter is operating in discontinuous conduction mode.

Note that continuous conduction mode includes the case in which synchronous (active) rectification is being used and the current through the coil is allowed to reverse direction when the output is lightly loaded. The output voltage in relation to the input voltage will still be defined by the switch duty cycle.

Therefore, we also know that the regulator in question is not using synchronous rectification, but rather is using a diode instead.

Problem 2
Since a diode can be placed in a High-Impedance state (reverse-biased) or a Low-Impedance state (forward-biased), they are sometimes used to switch AC signals, including audio and RF. What determines the magnitude of a signal that a diode can switch?

Answer 2
When diodes are used for signal switching, there are two considerations with regard to the magnitude of the signal relative to the DC control signal:

  • In the Blocking state, the reverse bias voltage must be greater than the peak signal voltage to prevent signal leakage. Also, a high-bias voltage reduces the parasitic capacitance through the diode. PIN diodes are often used for RF switching because of their ultra-low capacitance.
  • In the On state, the forward DC control current through diode must be greater than the peak AC signal current, and it must be large enough so that the current doesn’t approach the diode curve’s “knee” too closely, introducing distortion.

Obviously, the diode needs to be rated for both the peak reverse voltage and the peak forward current created by the combination of the control signal and the application signal.

Problem 3
What common function does the following truth table represent?

A B C X Y Z
0 0 0 ? 0 0 0
0 0 1 ? 0 0 1
0 1 0 ? 0 1 0
0 1 1 ? 0 0 1
1 0 0 ? 1 0 0
1 0 1 ? 0 0 1
1 1 0 ? 0 1 0
1 1 1 ? 0 0 1

Answer 3
The truth table implements a form of priority encoder:

Z is set if C is set, otherwise
Y is set if B is set, otherwise
X is set if A is set

In other words, C has the highest priority and A has the lowest. However, unlike conventional priority encoders that produce a binary output, this one produces a “one hot” encoding.

Problem 4
Write the equations for the logic that would implement the table.

Answer 4
The logic is quite straightforward:

Z = C
Y = B & !C
X = A & !B & !C

Issue 274: EQ Answers

The answers to the Circuit Cellar 274 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—What is wrong with the name “programmable unijunction transistor?”

Answer 1—Unlike the original unijunction transistor—which really does have just a single junction—the programmable unijunction transistor (PUT) is actually a four-layer device that has three junctions, much like a silicon-controlled rectifier (SCR).

 

Problem 2—Given a baseband channel with 3-kHz bandwidth and a 40-dB signal-to-noise ratio (SNR), what is the theoretical capacity of this channel in bits per second?

Answer 2—The impulse response of an ideal channel with exactly 3 kHz of bandwidth is a sinc (i.e., sin(x)/x) pulse in the time domain that has nulls that are 1/6,000 s apart. This means you could send a series of impulses through this channel at a 6,000 pulses per second rate. And, if you sampled at exactly the correct instants on the receiving end, you could recover the amplitudes of each of those pulses with no interference from the other pulses on either side of it.

However, a 40-dB signal-to-noise ratio implies that the noise power is 1/10,000 of the maximum signal power. In terms of distinguishing voltage or current levels, this means you can send at most sqrt(10,000) = 100 distinct levels through the channel before they start to overlap, making it impossible to separate one from another at the receiving end.

100 levels translates to log2100 = 6.64 binary bits of information. This means the total channel capacity is 3,9840 bits/s (i.e., 6,000 pulses/s × 6.64 bits/pulse).

This is the basis for the Shannon-Hartley channel capacity theorem.

 

Problem 3—In general, is it possible to determine whether a system is linear and time-invariant (LTI) by simply examining its input and output signals?

Answer 3—In general, given an input signal and an output signal, you might be able to definitively state that the system is not linear and time-invariant (LTI), but you’ll never be able to definitively state that it is, only that it might be.

The general technique is to use information in the input signal to see whether the output signal can be composed from the input features. Input signals (e.g., impulses and steps) are easist to analyze, but other signals can also be analyzed.

 

Problem 4—One particular system has this input signal:

Figure 1

The output is given by:

Figure 2

Is this system LTI?

Answer 4—In this example, the input is a rectangular pulse that can be analyzed as the superposition of two step functions that are separated in time, one positive-going and the other negative-going. This makes the analysis easy, since you can see the initial response to the first step function then determine whether the response following the second step is a linear combination of two copies of the first part of the response.

In this case, the response to the first step function at t = 0 is that the output starts rising linearly, also at t = 0. The second (negative) input step function occurs at t = 0.5, and if the system is LTI, you would expect the output to also change what it’s doing at that time. In fact, you would expect the output to level off at whatever value it had reached at that time, because the LTI response to the second step should be a negative-going linear ramp, which, when added to the original response, should cancel out.

However, this is not the output signal received, so this system is definitely not LTI.

Issue 272: EQ Answers

The answers to the Circuit Cellar 272 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—Why does the power dissipation of a Darlington transistor tend to be higher than that of a single bipolar transistor in switching applications?

Answer 1—In switching applications, a single transistor can saturate, resulting in a low VCE of 0.3 to 0.4 V. However, in a Darlington pair, the output transistor is prevented from saturating by the negative feedback provided by the driver transistor. If the collector voltage drops below the sum of the VBE of the output transistor (about 0.7 V) and the VCE(sat) of the driver transistor (about 0.3 V), the drive current to the output transistor is reduced, preventing it from going into saturation itself. Therefore, the effective VCE(sat) of the Darlington pair is 1 V or more, resulting in much higher dissipation at a given current level.

Problem 2—Suppose you have some 3-bit data, say, grayscale values for which 000 = black and 111 = white. You have a display device that takes 8-bit data, and you want to extend the bit width of your data to match.

If you just pad the data with zeros, you get the value 11100000 for white, which is not full white for the 8-bit display—that would be 11111111. What can you do?

Answer 2—One clever trick is to repeat the bits you have as many times as necessary to fill the output field width. For example, if the 3-bit input value is ABC, the output value would be ABCABCAB. This produces the following mapping, which interpolates nicely between full black and full white (see Table 1). Note that this mapping preserves the original bits; if you want to go back to the 3-bit representation, just take the MSBs and you have the original data.

3-bit INPUT 8-bit OUTPUT
000 00000000
001 00100100
010 01001001
011 01101101
100 10010010
101 10110110
110 11011011
111 11111111

Problem 3—Can an induction motor (e.g., squirrel-cage type) be used as a generator?

Answer 3—Believe it or not, yes it can.

An induction motor has no electrical connections to the rotor; instead, a magnetic field is induced into the rotor by the stator. The motor runs slightly slower than “synchronous” speed—typically 1725 or 3450 rpm when on 60 Hz power.

If the motor is provided with a capacitive load, is driven at slightly higher than synchronous speed (1875 or 3750 rpm), and has enough residual magnetism in the rotor to get itself going, it will generate power up to approximately its rating as a motor. The reactive current of the load capacitor keeps the rotor energized in much the same way as when it is operating as a motor.

See www.qsl.net/ns8o/Induction_Generator.html for additional details.

Problem 4—In Figure 1, why does this reconstruction of a 20-kHz sinewave sampled at 44.1 kHz show ripple in its amplitude?

Answer 4—The actual sampled data, represented by the square dots in the diagram, contains equal levels of Fsignal (the sine wave) and Fsample-Fsignal (one of the aliases of the sinewave). Any reconstruction filter is going to have difficulty passing the one and eliminating the other, so you inevitably get some of the alias signal, which, when added to the desired signal, produces the “modulation” you see.

In the case of a software display of a waveform on a computer screen (e.g., such as you might see in software used to edit audio recordings), they’re probably using an FIR low-pass filter (sin(x)/x coefficients) windowed to some finite length. A shorter window gives faster drawing times, so they’re making a tradeoff between visual fidelity and interactive performance. The windowing makes the filter somewhat less than brick-wall, so you get the leakage of the alias and the modulation.

In the case of a real audio D/A converter, even with oversampling you can’t get perfect stopband attenuation (and you must always do at least some of the filtering in the analog domain), so once again you see the leakage and modulation.

In this example, Fsignal = 0.9×Fnyquist, so Falias = 1.1×Fnyquist and Falias/Fsignal = 1.22. To eliminate the visible artifacts, the reconstruction filter would need to have a slope of about 60dB over this frequency span, or about 200 dB/octave.

Issue 270: EQ Answers

The answers to the Circuit Cellar 270 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1: Given a microprocessor that has hardware support for just one level of priority for interrupts, is it possible to implement multiple priorities in software? If so, what are the prerequisites that are required?

Answer 1: Yes, given a few basic capabilities, it is possible to implement multiple levels of interrupt priority in software. The basic requirements are that it must be possible to reenable interrupts from within an interrupt service routine (ISR) and that the different interrupt sources can be individually masked.

Question 2: What is the basic scheme for implementing software interrupt priorities?

Answer 2: In normal operation, all the interrupt sources are enabled, along with the processor’s global-interrupt mask.

When an interrupt occurs, the global interrupt mask is disabled and the “master” ISR is entered. This code must (quickly) determine which interrupt occurred, disable that interrupt and all lower-priority interrupts at their sources, then reenable the global-interrupt mask before jumping to the ISR for that interrupt. This can often be facilitated by precomputing a table of interrupt masks for each priority level.

Question 3: What are some of the problems associated with software interrupt priorities?

Answer 3: For one thing, the start-up latency of all the ISRs is increased by the time spent in the “master” ISR. This can be a problem in time-critical systems. This scheme enables interrupts to be nested, so the stack must be large enough to handle the worst-case nesting of ISRs, on top of the worst-case nesting of non-interrupt subroutine calls.

Finally, it is very tricky to do this in anything other than Assembly language. If you want to use a high-level language, you’ll need to be intimately familiar with the language’s run-time library and how it handles interrupts and reentrancy, in general.

Answer 4: Yes, on most such processors, you can execute a subroutine call to a “return from interrupt” instruction while still in the master ISR, which will then return to the master ISR, but with interrupts enabled.

Check to see whether the “return from interrupt” affects any other processor state (e.g., popping a status word from the stack) and prepare the stack accordingly.

Also, beware that another interrupt could occur immediately thereafter, and make sure the master ISR is reentrant beyond that point.

 

Contributed by David Tweed

Electrical Engineering Tools & Preparation (CC 25th Anniversary Issue Preview)

Electrical engineering is frequently about solving problems. Success requires a smart plan of action and the proper tools. But as all designers know, getting started can be difficult. We’re here to help.

You don’t have to procrastinate or spend a fortune on tools to start building your own electronic circuits. As engineer/columnist Jeff Bachiochi has proved countless times during the past 25 years,  there are hardware and software tools that fit any budget. In Circuit Cellar‘s 25th Anniversary issue, he offers some handy tips on building a tool set for successful electrical engineering. Bachiochi writes:

In this essay, I’ll cover the “build” portion of the design process. For instance, I’ll detail various tips for prototyping, circuit wiring, enclosure preparation, and more. I’ll also describe several of the most useful parts and tools (e.g., protoboards, scopes, and design software) for working on successful electronic design projects. When you’re finished with this essay, you’ll be well on your way to completing a successful electronic design project.

The Prototyping Process

Prototyping is an essential part of engineering. Whether you’re working on a complicated embedded system or a simple blinking LED project, building a prototype can save you a lot of time, money, and hassle in the long run. You can choose one of three basic styles of prototyping: solderless breadboard, perfboard, and manufactured PCB. Your project goals, your schedule, and your circuit’s complexity are variables that will influence your choice. (I am not including styles like flying leads and wire-wrapping.)

Prototyping Tools

The building phase of a design might include wiring up your circuit design and altering an enclosure to provide access to any I/O on the PCB. Let’s begin with some tools that you will need for circuit prototyping.

The nearby photo shows a variety of small tools that I use when wiring a perfboard or assembling a manufactured PCB. The needle-nose pliers/cutter is the most useful.

These are my smallest hand tools. With them I can poke, pinch, bend, cut, smooth, clean, and trim parts, boards, and enclosures. I can use the set of special driver tips to open almost any product that uses security screws.

Don’t skimp on this; a good pair will last many years. …

Once everything seems to be in order, you can fill up the sockets. You might need to provide some stimulus if you are building something like a filter. A small waveform generator is great for this. There are even a few hand probes that will provide outputs that can stimulate your circuitry. An oscilloscope might be the first “big ticket” item in which you invest. There are some inexpensive digital scope front ends that use an app running on a PC for display and control, but I suggest a basic analog scope (20 MHz) if you can swing it (starting at less than $500).

If the circuit doesn’t perform the expected task, you should give the wiring job a quick once over. Look to see if something is missing, such as an unconnected or misconnected wire. If you don’t find something obvious, perform a complete continuity check of all the components and their connections using an ohmmeter.

I use a few different meters. One has a transistor checker. Another has a high-current probe. For years I used a small battery-powered hand drill before purchasing the Dremel and drill press. The tweezers are actually an SMT parts measurer. Many are unmarked and impossible to identify without using this device (and the magnifier).

It usually will be a stupid mistake. To do a complete troubleshooting job, you’ll need to know how the circuit is supposed to work. Without that knowledge, you can’t be expected to know where to look and what to look for.

Make a Label

You’ll likely want to label your design… Once printed, you can protect a label by carefully covering it with a single strip of packing tape.

The label for this project came straight off a printer. Using circuit-mount parts made assembling the design a breeze.

A more expensive alternative is to use a laminating machine that puts your label between two thin plastic sheets. There are a number of ways to attach your label to an enclosure. Double-sided tape and spray adhesive (available at craft stores) are viable options.”

Ready to start innovating? There’s no time like now to begin your adventure.

Check out the upcoming anniversary issue for Bachiochi’s complete essay.