New STM32 Micrcontrollers in Small Memory Sizes

STMicroelectronics’s new STM32F446 microcontrollers feature ARM Cortex-M4 based processing combined with 256- or 512-KB on-chip flash memory options. In addition to using STMicro’s ART Accelerator, the microcontrollers feature smart architecture, advanced flash technology, and an embedded ARM Cortex-M4 core to achieve a performance of 225 DMIPS and 608 CoreMark at 180 MHz executing from embedded flash.

Source: STMicroelectronics

Source: STMicroelectronics

Key features include:

  • At 180 MHz, the STM32F446 delivers 225 DMIPS/608 CoreMark performance executing from flash memory with 0-wait states. The DSP instructions and the floating-point unit expand the range of addressable applications.
  • Using a 90-nm process, the current consumption in Run mode and executing from flash memory is as low as 200 µA/MHz at 180 MHz. In Stop mode, the power consumption is 50 µA typical.
  • Two dedicated audio PLL, SPDIF input, three half-duplex I²S, and two serial audio interfaces (SAI) supporting full-duplex I²S as well as time division multiplex (TDM) mode.
  • Up to 20 communication interfaces (including 4x USARTs plus 2x UARTs running at up to 11.25 Mbps, 4x SPI running at up to 45 Mbps, 3x I²C with a new optional digital filter capability, 2x CAN, SDIO, HDMI CEC and camera interface)
  • Two 12-bit DACs, three 12-bit ADCs reaching 2.4 MSPS or 7.2 MSPS in interleaved mode up to 17 timers: 16- and 32-bit running at up to 180 MHz
  • Easily extendable memory range using the flexible 90-MHz memory controller with a 32-bit parallel interface, and supporting Compact Flash, SRAM, PSRAM, NOR, NAND and SDRAM memories
  • Cost-effective NOR flash extension with the 90-MHz Dual quadSPI interface supporting memory-mapped mode
  • STM32F446 samples are now available for lead customers. Volume production is scheduled for Q1 2015 in packages from a tiny WLCSP81 measuring 3.728 × 3.85 mm to a 20 × 20 mm LQFP144 with 256- or 512-KB flash memory, all with 128-KB SRAM. Pricing starts at $3.75 for the STM32F446RC in a 64-pin LQFP64 package with 256-KB flash memory and 128-KB SRAM for orders of 10,000 units.

Source: STMicroelectronics

STMicro Reduces Time to Development with Open.MEMS Licensing

STMicroelectronics recently announced the launch of the Open.MEMS licensing program. Its purpose is to encourage broad use of its MEMS and sensors among open-community developers. Open.MEMS licensees can access free drivers, middleware, and application software, beginning with “sensor fusion for 3-axis accelerometer, 3-axis gyroscope, and 3-axis magnetometer, considered vital for many portable and wearable applications.”

STMicro’s STM32 Open Development platform supports Open.MEMS, which went live on November 11, 2014, and will continue to be expanded regularly with additional low-level drivers, middleware/libraries, and application-layer code.

 

DIY Network-Ready Polyphonic Music Controller

Hans Peter Portner’s Chimaera project is a touch-less, expressive, network-ready, polyphonic music controller released as open source hardware. It is a mixed analog/digital offspring of the Theremin. An array of analog, linear Hall effect sensors make up a continuous 2-D interaction space. The sensors are excited with Neodymium magnets worn on fingers.

Portner's Chimaera project

Portner’s Chimaera project

The device continuously tracks and interpolates position and vicinity of multiple present magnets along the sensor array to produce corresponding low-latency event signals. Those are encoded as Open Sound Control bundles and transmitted via UDP/TCP to a software synthesizer. The DSP unit is a mixed-signal board and handles sensor read out, event detection and host communication. It is based on an ARM Cortex M4 microcontroller in combination with WIZnet W5500 chip, which takes care of all low-level networking protocols via UDP/TCP.

First Prize — Chimaera: The Poly-Magneto-Phonic Theremin, Hans Peter Portner (Switzerland)

The poly-magneto-phonic Theremin

In his project write-up, Portner explains:

With its touch-less control (no friction), high update rates (2-4 kHz), its quasi-continuous spatial resolution and its low-latency (<1 ms), the Chimaera can react to most subtle motions instantaneously and allows for a highly dynamic and expressive play. Its open source design additionally gives the user all possibilities to further tune hardware and firmware to his or her needs. The Chimaera is network-oriented and configured with and communicated by Open Sound Control, which makes it straight-forward to integrate into any setup.

The hardware of the Chimaera consists of two types of printed circuit boards and an enclosure. Multiple sensor units are daisy-chained to form the sensor array and connected to a single digital signal processing (DSP) unit.

Sensor unit

Sensor unit

A single sensor unit consists of 16 linear hall-effect sensors spaced 5mm apart and routed to a single output through a 16:1 multiplexer which is switched by the DSP unit. Downstream the multiplexer, the analog signal runs through an amplification circuitry.

A modular hardware design consisting of identical sensor units and a single DSP unit embedded in a wooden case allows building devices with array sizes of 16-160 sensors.
A modular hardware design consisting of identical sensor units and a single DSP unit embedded in a wooden case allows building devices with array sizes of 16-160 sensors.

The DSP unit is a mixed-signal board and handles sensor read out, event detection and host communication. It is based on an STM32F303Cx ARM Cortex M4 microcontroller in combination with WIZnet W5500, a hardwired 100Mbit IPv4/PHY chip taking care of all low-level networking protocols via UDP/TCP. The board’s analog part features 10 analog inputs providing connection points for the sensor units, leading to a maximally possible array of 160 sensors. Those analog inputs connect directly to three in parallel running 12bit analog-to-digital converters.

Schematic of the DSP unit (STM32F303Cx part)

Schematic of the DSP unit (STM32F303Cx part)

Networking technology in a zero configuration setup has advantages in respect to long-distance transmission, operating system independence and inherent ability for network performances. We thus use the Open Sound Control (OSC) specification via UDP/TCP as low-level communication layer.

Schematic of the DSP unit (WIZnet W5500 part)

Schematic of the DSP unit (WIZnet W5500 part)

Portner’s project won First Prize in the WIZnet Connect the Magic 2014 Design Challenge. The entire project and its associated files are now available.

Q&A: Electrical Engineer & FPGA Enthusiast

Chris Zeh is a San Jose, CA-based hardware design engineer who enjoys working with FPGA development boards, application-specific integrated circuits, and logic analyzers. He recently told us about the projects he is involved with at STMicroelectronics and explained what he’s working on in his free time.

CIRCUIT CELLAR: Tell us about Idle-Logic.com. Why and when did you decide to start a blog?

ZehCHRIS: I started blogging in the winter of 2009, a little more than a year after I graduated Colorado State University with a BSEE. I realized that after graduating it was important to continue working on various projects to keep my mind and skills sharp. I figured the best way to chronicle and show off my projects was to start a blog—my little corner of the Internet.

CIRCUIT CELLAR: What types of projects do you feature on your site?

CHRIS: I like working on a wide range of different types of projects, varying from software development to digital and analog design. I’ve found that most of my projects highlighted on Idle-Logic.com have been ones focusing on FPGAs. I find these little reprogrammable, multipurpose ICs both immensely powerful and fascinating to work with.

My initial plan for the blog was to start a development project to create an FPGA equivalent to the Arduino. I wanted to build a main board with all the basic hardware to run an Altera Cyclone II FPGA and then create add-on PCBs with various sensors and interfaces. My main FPGA board was to be named the Saturn board, and the subsequent add-on “wings” were to be named after the various moons of Saturn.

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

The project proceeded nicely. I spent some time brushing up on my Photoshop skills to put together a logo and came up with a minimized BOM solution to provide power to the nine different voltage supplies, both linear regulators and switched-mode supplies. One aspect of FPGAs that can make them costly for hobbyist is that the programming JTAG cable was on the order of $300. Fortunately, there are a few more affordable off-brand versions, which I used at first. After many weeks of work, I finally had the total solution for the main FPGA board. The total cost of the prototype system was about $150. Eventually I came up with a way to bit bang the FPGA’s programming bitstream using a simple $15 USB-to-UART IC breakout board driven by a tiny Python application, eliminating the need for the pricey cable. This Future Technology Devices International FT232RL USB-to-UART IC also provided a clock output enabling me to further reduce the component count.

The project was a success in that I was compelled to completely digest the FPGA’s 470-page handbook, giving me a solid grasp of how to work with FPGAs such as the Cyclone II. The project was a failure in that the FPGA breakout board I wanted to use for the project was discontinued by the manufacturer. Creating and fabricating my own four-layer board and hand soldering the 208-pin package was both prohibitively expensive and also a little daunting.

Fortunately, at that time Terasic Technologies introduced its DE0-Nano, a $79 commercial, $59 academic, feature-packed FPGA evaluation board. The board comes with two 40-pin general I/O plus power headers, which has become a perfect alternative base platform for FPGA development. I now intend to develop add-on “wings” to work with this evaluation board.

CIRCUIT CELLAR: Tell us more about how you’ve been using Terasic Technologies’s DE0-Nano development and education board.

CHRIS: The main project I’ve been working on lately with the DE0-Nano is creating and adding support for a full-color 4.3” (480 × 272 pixel) thin- film transistor (TFT) touchscreen LCD. Because of the large pin count available and reconfigurable logic, the DE0-Nano can easily support the display. I used a Waveshare Electronics $20 display, which includes a 40-pin header that is almost but not quite compatible with the DE0-Nano’s 40-pin header. Using a 40-pin IDC gray cable, I was able to do some creative rewiring (cutting and swapping eight or so pins) to enable the two to mate with minimal effort. Eventually, once all the features are tested, I’ll fabricate a PCB in place of the cable.

There are many libraries available to drive the display, but for this project I want to develop the hardware accelerators and video pipeline from the ground up, purely though digital logic in the FPGA. I recently picked up an SD card breakout board and a small camera breakout board. Using these I would like to start playing around with image processing and object recognition algorithms.

CIRCUIT CELLAR: What do you do at STMicroelectronics and what types of projects are you working on?

CHRIS: My official title is Senior Hardware Design Engineer. This title mainly comes thanks to the first project I worked on for the company, which is ongoing—an FPGA-based serial port capture and decoding tool named the HyperSniffer. However, my main role is that of an application engineer.

I spend most of my time testing and debugging our prototype mixed-signal ASICs prior to mass production. These ASICs are built for the hard disk drive industry. They provide several switch-mode power supplies, linear regulators, brushless DC motor controllers, voice coil motor actuation, and a shock sensor digital processing chain, along with the various DACs, ADCs, and monitoring circuits all integrated into a single IC.

Our ASIC’s huge feature set requires me to stay sharp on a wide variety of topics, both analog and digital. A typical day has me down in the lab writing scripts in Python or Visual Studio, creating stimuli, and taking measurements using my 1-GHz, 10-GSPS LeCroy WavePro 7100A oscilloscope, several 6.5-digit multimeters, dynamic signal analyzers, and noise injection power supplies among other instruments. I work closely with our international design team and our customers to help discover and document bugs and streamline the system integration.

A few years back I was able to join my colleagues in writing “Power Electronics Control to Reduce Hard Disk Drive Acoustics Pure Tones,” an Institute of Electrical and Electronics Engineers (IEEE) paper published for the Control and Modeling for Power Electronics (COMPEL) 2010 conference. I presented the paper, poster, and demonstration at the conference discussing a novel technique to reduce acoustic noise generated by a spindle motor.

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent Himpe and Albino Miglialo.)

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent
Himpe and Albino Miglialo.)

CIRCUIT CELLAR: Tell us more about the HyperSniffer project.

CHRIS: The HyperSniffer project is an FPGA- based digital design project I first created right out of college. (My colleagues Vincent Himpe and Albino Miglialo did the board design and layout.) The tool is basically an application-specific logic analyzer. It enables us to help our customers troubleshoot problems that arise from serial port transmissions between their system-on-a-chip (SoC) and our ASIC. Through various triggering options it can collect and decode the two or three wire data transmissions, store them on on- board memory, and wait for retrieval and further processing by the application running on the PC. One of this tool’s nice features is that it is capable of synchronizing and communicating with an oscilloscope, enabling us to track down problems that happen in the analog domain that arise due to commands sent digitally.

You can read the entire interview in Circuit Cellar 290 (September 2014).

New JANSR+ 100krad Transistors for Radiative Environments

STMicroelectronics recently announced it is bringing into the JANS system the innovation released last year within the European Space Components Coordination (ESCC) program. Called JANSR+, the innovation consists of a series of 100krad JANSR high-dose-rate bipolar transistors with an additional 100krad low-dose-rate (100 mrad/s) test performed on each wafer.rad_hard_bipolar_trans

Furthermore, ST has announced it will complete its JANSR+ offer with data from very-low-dose-rate (10 mrad/s) tests, demonstrating the outstanding robustness to radiation effect of its technology.

As a result, ST’s JANSR+ series gives access to products with superior performance in radiative environments, with complete test data to support the claim. These products can be used without any up-screen cost and lead time, thus dramatically raising the bar in the industry.

All parts are housed in advanced hermetic UB packages and are available in sample and volume quantities.

[Via STMicroelectronics]