2014 SoC Conference Early Bird Registration Now Open

Early Bird Registration is now open for the 12th International System on a Chip (SoC) Conference, which will take place at the University of California, Irvine (UCI) from October 22–23, 2014. Early Bird Registration ends October 10, 2014.

The conference will include technical presentations, exhibits, networking opportunities, panel discussions, and keynotes.

About the conference:

  • Keynotes
    • Dr. Takahiro Hanyu, New Paradigm VLSI System Research Group, Laboratory for Brainware Systems Research Institute of Electrical Communication, Tohoku University, Japan
    • Jim Aralis, Chief Technology Officer (CTO), and Vice President of R&D,  Microsemi
    • Dr. Peter L. Gammel, Chief Technology Officer (CTO), Skyworks Solutions, Inc.
    • Hughes Metras, VP, Strategic Partnerships CEA-LETI, France.
  • Special IC Technology Tutorial
    • “IC Technology at New Nodes Made Easy!,” Dr. Alvin Loke, IEEE Solid-State Circuits Distinguished Lecturer, Qualcomm Technologies, Inc.
  • Sessions
    • “Optical Computing with Silicon Photonics.” Yunshan Jiang, Peter DeVore, Jacky Chan, Bahram Jalali, UCLA
    • “Widely Tunable MMMB Wireless Front-Ends Using RF-CMOS MEMS,” Jeffrey L. Hilbert, CEO & Founder, WiSpry, Inc.
    • “Packaging and Assembly for Internet of Things Electronics: SoC Performance at SiP Cost,” Dr. Jayna Sheats, CEO, Terecircuits
    • “Full SoC Emulation from Device Drivers to Peripheral Interfaces,” Jim Kenney, Marketing Director for Mentor Mentor Graphics’ Emulation Division
    • And more.

Source: 2014 SoC Conference

 

SmartFusion2 Advanced Dev Kit

Microsemi Corp. has announced a new larges-density, low-power SmartFusion2 150K LE SoC FPGA Advanced Development Kit. It’s meant for board-level designers and system architects who need to rapidly create system-level designs.

Source: Microsemi Corp.

Source: Microsemi Corp.

The kit’s features include:

  • Largest 150K LE development device
  • 2x FMC connectors (HPC and LPC)
  • Purchase of kits comes with a free one-year Libero SoC design software platinum license (valued at $2,500)
  • DDR3, SPI flash
  • 2× Gigabit Ethernet connectors
  • SMA connectors
  • PCIe x4 edge connector
  • Power measurement test points

Source: Microsemi

 

Windows-Compatible Dev Board

Intel, Microsoft, and Circuit Co. have teamed up to produce a development board designed for the production of software and drivers used on mobile devices such as phones, tablets and similar System on a Chip (SoC) platforms running Windows and Android operating systems with Intel processors.

Source: SharksCove.org

Source: SharksCove.org

The 6″ × 4″ Sharks Cove board and features a number of interfaces including GPIO, I2C, I2S, UART, SDIO, mini USB, USB, and MIPI for display and camera.

Its main features include:

  • Intel  ATOM Processor Z3735G , 2M Cache, 4 Core, 1.33 GHz up
    to 1.88 GHz
  • Intel HD Graphics
  • 1 GB 1×32 DDR3L-RS-1333, 16-GB EMMC storage, micro SD Card
  • HDMI full size connector, MIPI display connector
  • Twelve (5 × 2) Shrouded pin header connectors, 1 (2 × 10) sensor header, 2 × 60 pin MIPI connector for display, camera and 5 (2 × 2) headers for power
  • One USB 2.0 type A connector
  • One micro USB type A/B for debug
  • Audio Codec Realtek ALC5640, speaker output header and onboard digital mic
  • Ethernet or WiFi via USB
  • Intel UEFI BIOS
  • Power, volume up, volume down, home screen and rotation lock
  • One micro USB type A/B for Power
  • SPI debug programming header

You can preorder the board for $299. It includes a Windows 8.1 image together with all the necessary utilities for it to run on Sharks Cove.

Kernel RTOS Evaluation Kit

eSOL has started offering the eT-Kernel Evaluation Kit for Xilinx’s Zynq-7000 All Programmable SoC, which combines the dual-core ARM Cortex-A9 MPCore processor with Xilinx’s 28-nm programmable logic fabric. The Evaluation Kit integrates eSOL’s eT-Kernel Multi-Core Edition real time operating system (RTOS), its dedicated eBinder integrated development environment (IDE), middleware components, and device drivers. This complimentary 30-day Evaluation Kit permits developers to easily and quickly evaluate the performance and quality of Xilinx Zynq-7000 All Programmable SoC and eT-Kernel. Since eT-Kernel inherited the functions and architecture of uITRON, the most popular RTOS in Japan and Asian countries, developers can reuse their uITRON-based software assets without further work.

Run-time software in the Evaluation Kit includes the eT-Kernel Multi-core Edition, eSOL’s PrFILE2 FAT file system, the SD memory card driver, and the HDMI display driver, all of which are integrated and immediately run on the Zynq-7000 All Programmable SoC Evaluation Board. The eBinder IDE is available for eT-Kernel Multi-Core Edition-based software development. Besides ARM’s genuine compiler, eBinder offers various development tools and functions to strongly support multi-programming, debugging, and analysis for complex multi-core software development.

Zynq-7000 All Programmable SoC tightly integrates two ARM Cortex-A9 MPCore processors and FPGA fabric. The hardware and software programmability of Zynq-7000 AP SoC enables system development with high performance, flexibility, and scalability, while achieving lower power consumption and cost.

The eT-Kernel/Zynq-7000 All Programmable SoC Evaluation Kit allows developers to jump-start their evaluation using packaged device drivers, which saves the time and money of developing them. Zynq-7000 All Programmable SoC and the eT-Kernel Platform are an ideal combination for advanced embedded systems in the automotive, industrial, and medical arenas, including Automotive Driver Assistance Systems (ADAS), high-resolution graphic systems, machine vision systems, and network systems.

[Source: eSOL Co., Ltd]

8-Bit Microcontroller IP Core

DigitalCoreDesignThe DF6808 IP core is binary-compatible with the industry-standard Motorola 68HC08 8-bit microcontroller. The IP core uses sophisticated on-chip peripheral capabilities to perform 45 to 100 million instructions per second. FAST architecture implemented in DF6808 enables the 68HC08 microcontroller to run at least three times faster than the original solution.

The DF6808’s 16-bit, free-running timer system has two input-capture lines and two output-compare lines. The IP core is equipped with proprietary safety functions, including self-monitoring circuitry, which helps protect against system errors; the computer operating properly (COP) watchdog system, which protects against software failures; and an illegal opcode detection circuit, which provides a non-maskable interrupt if an illegal opcode occurs.

For power conservation, the IP core includes two software-controlled power-saving modes (Wait and Stop). These modes make the DF6808 IP core well suited for automotive and battery-driven applications.

The DF6808 includes the DoCDTM real-time hardware debugger, which provides built-in support for Digital Core Design’s hardware debug system and the debugging capability of an entire system-on-a-chip (SoC). The DoCDTM enables nonintrusive debugging of running applications. It can halt, run, step into, or skip an instruction and read/write any microcontroller contents, including all registers, user-defined peripherals, data, and program memories.

Contact Digital Core Design for pricing.

Digital Core Design
www.dcd.pl