The Future of Monolithically Integrated LED Arrays

LEDs are ubiquitous in our electronic lives. They are widely used in notification lighting, flash photography, and light bulbs, to name a few. For displays, LEDs have been commercialized as backlights in televisions and projectors. However, their use in image formation has been limited.

A prototype emissive LED display chip is shown. The chip includes an emissive compass pattern ready to embed into new applications.

A prototype emissive LED display chip is shown. The chip includes an emissive compass pattern ready to embed into new applications.

The developing arena of monolithically integrated LED arrays, which involves fabricating millions of LEDs with corresponding transistors on a single chip, provides many new applications not possible with current technologies, as the LEDs can simultaneously act as the backlight and the image source.

The common method of creating images is to first generate light (using LEDs) and then filter that light using a spatial light modulator. The filter could be an LCD, liquid crystal on silicon (LCoS), or a digital micromirror device (DMD) such as a Digital Light Processing (DLP) projector. The filtering processes cause significant loss of light in these systems, despite the brightness available from LEDs. For example, a typical LCD uses only 1% to 5% of the light generated.

Two pieces are essential to a display: a light source and a light controller. In most display technologies, the light source and light control functionalities are served by two separate components (e.g., an LED backlight and an LCD). However, in emissive displays, both functionalities are combined into a single component, enabling light to be directly controlled without the inherent inefficiencies and losses associated with filtering. Because each light-emitting pixel is individually controlled, light can be generated and emitted exactly where and when needed.

Emissive displays have been developed in all sizes. Very-large-format “Times Square” and stadium displays are powered by large arrays of individual conventional LEDs, while new organic LED (OLED) materials are found in televisions, mobile phones, and other micro-size applications. However, there is still a void. Emissive “Times Square” displays cannot be scaled to small sizes and emissive OLEDs do not have the brightness available for outdoor environments and newer envisioned applications. An emissive display with high brightness but in a micro format is required for applications such as embedded cell phone projectors or displays on see-through glasses.

We know that optimization by the entire LED industry has made LEDs the brightest controllable light source available. We also know that a display requires a light source and a method of controlling the light. So, why not make an array of LEDs and control individual LEDs with a matching array of transistors?

The marrying of LED materials (light source) to transistors (light control) has long been researched. There are three approaches to this problem: fabricate the LEDs and transistors separately, then bond them together; fabricate transistors first, then integrate LEDs on top; and fabricate LEDs first, then integrate transistors on top. The first method is not monolithic. Two fabricated chips are electrically and mechanically bonded, limiting integration density and thus final display resolutions. The second method, starting with transistors and then growing LEDs, offers some advantages in monolithic (single-wafer) processing, but growth of high-quality, high-efficiency LEDs on transistors has proven difficult.

My start-up company, Lumiode (www.lumiode.com), is developing the third method, starting with optimized LEDs and then fabricating silicon transistors on top. This leverages existing LED materials for efficient light output. It also requires careful fabrication of the integrated transistor layer as to not damage the underlying LED structures. The core technology uses a laser method to provide extremely local high temperatures to the silicon while preventing thermal damage to the LED. This overcomes typical process incompatibilities, which have previously held back development of monolithically integrated LED arrays. In the end, there is an array of LEDs (light source) and corresponding transistors to control each individual LED (light control), which can reach the brightness and density requirements of future microdisplays.

Regardless of the specific integration method employed, a monolithically integrated LED and transistor structure creates a new range of applications requiring higher efficiency and brightness. The brightness available from integrated LED arrays can enable projection on truly see-through glass, even in outdoor daylight environments. The efficiency of an emissive display enables extended battery lifetimes and device portability. Perhaps we can soon achieve the types of displays dreamed up in movies.

The Future of Nanotube Computing

For decades, silicon-based transistors have been the workhorse of the semiconductor industry, achieving remarkable advances in computational power. While advances continue to be made, alternative technologies are being explored to increase computational power and efficiency beyond the limits of silicon.

Carbon nanotubes (CNTs) are nanocylinders of carbon atoms, approximately 1 nm in diameter. They have amazing electrical, thermal, and physical properties. CNTs can be used to form CNT field-effect transistors (CNFETs), which use CNTs as the channel material of the transistor, with traditional lithographically defined sources, drains, and gates. It has been projected that digital systems made from carbon nanotubes can achieve more than an order of magnitude benefit in energy delay product (a common metric to compare a circuit’s performance and energy efficiency) compared to competing technologies.

However, it has been impracticable to realize these system-level benefits due to the inability to manufacture CNT-based circuits. This limitation stems from substantial imperfections inherent with the CNTs, including mispositioned and metallic CNTs. Mispositioned CNTs cause erroneous connections in a circuit, metallic (rather than semiconducting) CNTs decrease Ion/Ioff ratio, both potentially resulting in incorrect logic functionality and power wastage.

The trivial solution to these obstacles is to grow 100% perfectly aligned and semiconducting CNTs. However, this is currently infeasible, and likely never will be. Thus, to overcome these inherent imperfections, our Stanford University research team uses the imperfection-immune design paradigm. This paradigm combines processing solutions and design “tricks” to overcome these imperfections in the very-large-scale integration (VLSI) compatible manner.

Max Shulaker, a graduate student at Stanford University and author of this essay, holds a wafer filled with CNTs. (Photo: Norbert von der Groeben )

Max Shulaker, a graduate student at Stanford University and author of this essay, holds a wafer filled with CNTs. (Photo credit: Norbert von der Groeben )

We begin by growing the CNTs highly aligned. This is accomplished by growing the CNTs on a crystalline quartz substrate. The CNTs grow along the crystalline boundary of the quartz and result in highly aligned growths—99.5% alignment. However, for VLSI applications, there are millions or billions of transistors, resulting in billions of CNTs. Thus 99.5% is insufficient.

In addition, we employ mispositioned CNT immune design, which is a technique that renders the circuits that we make 100% immune to any mispositioned CNTs that would be left on the wafer. An important point is that the design is not dependent on the exact placement of the individual CNTs. It works for any arbitrary configuration of CNTs, and thus is manufacturable and scalable to very-large-scale circuits.

To remove metallic CNTs, we break them down, much like a fuse. We turn off all semiconducting CNTs in the circuit and pulse a large voltage across the transistors. Only the metallic CNTs conduct current, and by passing enough current, eventually heat up to

Max M. Shulaker, who holds a wafer filled with carbon nanotubes (CNTs), is a PhD candidate at Stanford University where he earned his BS in Electrical Engineering. He is part of a Stanford research team that recently built the first functioning computer using CNTs. Max works on experimentally demonstrating nanosystems with emerging technologies. His current research focuses on realizing increased levels of integration for CNT-based digital logic circuits. (Photo credit: Norbert von der Groeben)

Max M. Shulaker, who wrote this essay for Circuit Cellar, holds a wafer filled with carbon nanotubes (CNTs). Max is a PhD candidate at Stanford University where he earned his BS in Electrical Engineering. He is part of a Stanford research team that recently built the first functioning computer using CNTs. Max works on experimentally demonstrating nanosystems with emerging technologies. His current research focuses on realizing increased levels of integration for CNT-based digital logic circuits. (Photo credit: Norbert von der Groeben)

the point where they break down, much like a fuse. The trick is being able to perform this breakdown at a chip  scale. Computers today have billions of transistors. It would be infeasible to breakdown each transistor one by one. VLSI-compatible metallic CNT removal (VMR) is a design technique that enables the breakdown to be performed at an entire chip scale.

The imperfection-immune design paradigm, coupled with CNT-specific fabrication processing resulting in high-yield devices, permits, for the first time, the realization of larger-scale digital systems using this very promising technology. Most recently, a basic computer was fabricated at Stanford University completely using CNFETs. The CNT computer was composed of tens of thousands of CNTs, demonstrating the ability to manufacture CNT circuits in a scalable, and thus manufacturable, manner. The computer executes the subtract and branch if negative (SUBNEG) instruction, which is Turing complete, adding to the computer’s generality. As a demonstration, the CNT computer concurrently counted integers and sorted integers, continuously swapping between the two processes. To demonstrate the computer’s flexibility, it also emulated 20 different instructions from the commercial MIPS instruction set.

The CNT computer, culminating years of work by a team of researchers at Stanford University led by Professors Subhasish Mitra and Philip Wong, demonstrates that CNTs are a manufacturable and feasible technology. Beyond CNTs, it is a step forward for the broader field of emerging nanotechnologies. While many alternatives to silicon are being explored, the CNT computer represents an initial demonstration of one of these emerging technologies coming to fruition.

Can MoS2 Outperform Silicon?


Saptarshi Das

After decades of relentless progress, the evolutionary path of the silicon CMOS industry is finally approaching an end. Fundamental physical limitations do not enable silicon to scale beyond the 10-nm technology node without severely compromising a device’s performance. To reinforce the accelerating pace, there is an urgent and immediate need for alternative materials. Low-dimensional materials in general, and 2-D layered material in particular, are extremely interesting in this context. They offer unique electrical, optical, mechanical, and chemical properties. In addition, they feature excellent electrostatic integrity and inherent scalability, which makes them attractive from a technological standpoint. Graphene, hexagonal boron nitride (h-BN), and more recently the rich family of transition metal dichalcogenides—comprising Molybdenum disulfide (MoS2), WS2, WSe2, and many more—have received a lot of scientific attention as the future of nanoelectronics. The most widely studied material, grapheme, had reported intrinsic field effect mobility value as high as 10,000 cm2/Vs. However, the absence of an energy gap in the electronic band structure of grapheme, along with the challenges associated with making a stable interface with the gate dielectric, raises a lot of concern for grapheme-based nanoelectronics for logic applications. Hence, it paves the way for semiconducting 2-D materials such as MoS2 and others.

MoS2 is a stack of single layers held together by weak van der Waals interlayer interaction, and, therefore, enables micromechanical exfoliation of one or a few layers—similar to the fabrication of graphene from graphite. It is a semiconductor with an indirect bandgap of 1.2 eV. Single- and multilayer MoS2 field-effect transistors (FETs) with high on/off-current ratios (108) and excellent subthreshold swing (74 mV/decade) close to the ideal limit have been demonstrated. Basic integrated circuits (e.g., inverters and ring oscillators) have been reported. And initial studies also indicate that MoS2 has great potential in future nanoelectronics, sensing, and energy harvesting.

While there is a growing interest in MoS2-based nanoelectronics devices, the practice of evaluating their potential usefulness for electronic applications is still in its infancy since we don’t have a complete picture of their performance potential and scaling limits. My research addresses the major issues about the realization of high-performance logic devices based on ultra-thin MoS2 flakes. One of the major challenges in the realization of high-performance nano devices arises from the fact that these nanostructures need to be connected to the “outside” world to capitalize on their ultimate potential. Any interface between a low-dimensional nanostructure and a 3-D metal contact will inevitably affect the total system’s performance, which will strongly depend on the said contact’s quality. We have demonstrated that through a proper understanding and design of source/drain contacts and the right choice of the number of MoS2 layers to use, the excellent intrinsic properties of this 2-D material can be realized. Using scandium contacts on 10-nm-thick exfoliated MoS2 flakes that are covered by a 15-nm Al2O3 film, record high mobilities of 700 cm2/Vs are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. We have also investigated the ultimate scaling potential of multilayer MoS2 field effect transistors (FETs) with channel lengths ranging from 1 µm down to 50 nm. Our results indicate that the multilayer MoS2 FETs are extremely resilient to short channel effects. We have demonstrated record high drive current density of 2.5 mA/µm and record high transconductance of 500 µs/µm for a 50-nm-long MoS2 transistor, which are comparable to state-of-the-art silicon technology.

In short, MoS2 preserves all the important properties of silicon with the added advantage of an ultra-thin layer structure, which allows for aggressive channel length scaling down to 2 nm and, therefore, has the potential to outperform silicon beyond the 10-nm technology node. Properly nourishing the development of MoS2 can be a real game changer for the future of the micro- and nanoelectronics industry.—by Saptarshi Das, Circuit Cellar 270, January 2012