RISC-V and Moore’s Law : An Interview with Krste Asanovic

During his busy sabbatical, Krste Asanovic took time to share his thoughts on developments n the world of processors and the open sourcing of processor architecture.

Moore’s Law and the Chip Industry’s Perfect Storm

By Wisse Hettinga

With the end of Moore’s Law in sight and a silicon manufacturing world that is struggling to protect their investments, the RISC-V foundation is throwing its nets out on the other side of the boat. How? By creating an opensource platform for future new silicon development.

“There is a lot of friction in the market,” Asanovic explains. Being a professor at Berkeley University in Computer Architecture, he knows what he is talking about. “With RISC-V we want to reduce this friction in the industry. One of the problems is the IP protection and business involvement in the industry. With SiFive you don’t have to deal with complicated contracts. Users can just come and take the material that’s all published and open source and use it in their future chip design.”

Lead Opening Image

Krste Asanovic is a SiFive founder and Professor of Computer Architecture at Berkeley University.

“The Barcelona Computer Centre is showing great interest in what we are doing with RISC-V. And the UPC computer architecture department is one of the strongest architecture group in Europe. Here—and also in the rest of Europe—there is a lot of interest in RISC-V for research projects and also for possible industrial use,” says Asanovic.

HETTINGA: Can you explain what RISC-V is?

ASANOVIC: RISC-V is an instruction set architecture (ISA). An ISA is what you use to encode software to run on hardware. In the industry there are common standards like the x86 from Intel and AMD. There’s also the ARM architecture we all know from our mobile phones and tablets. RISC-V uses different encoding which is meant to be free and open so that everyone can use without paying license fee—which is unlike the existing proprietary standards. Our goal is to have an open standard anybody can use.

HETTINGA: And what’s the level of interest from the market today for RISC-V?

ASANOVIC: If you look at the market, the x86 architecture is dominant in desktops and servers. ARM is dominant in mobile phones and tablets—and it will probably remain so. But what is interesting is that there are always new markets coming along: IoT (Internet of Things) and automotive are big markets. At the high-end of the market we see storage controllers and machine learning accelerators. These are all new greenfield areas where people are looking at new chip designs. They don’t have a large legacy of software and they are open to a new instruction set—particularly ones that are free of all sorts of legal and financial strings and give them flexibility to bring new things into the controller architecture.

HETTINGA: Give us a little history of RISC and of RISC versus CISC.

ASANOVIC: The RISC architecture goes a long way back and it’s still alive. I trace the roots of RISC way back to Seymour Cray’s early machines—like the CDC 6600—from 1964. RISC machines are register rich and have a load/store architecture. They have a lot of general registers and all operations are between registers except for the memory operations. That style of machine has remained popular for over 50 years and has outlived Moore’s Law.

Meanwhile, CISC has also been around for some time. CISC was a product of the time before integrated silicon started replacing the vacuum tubes and magnetic core memory systems. It is interesting to see that over the last couple decades there has been very little new development in the CISC architecture arena. I think everyone will agree that if you start from scratch, CISC is not a great idea.

RISC-V follows the heritage of the earlier RISC processor designs developed at Berkeley University. “RISC-V” means it is the fifth generation. We started on the project in 2010 and we were tired of using commercial ISAs for research. They were sometimes too complicated for what we wanted to do, and with the IP entanglements it is very difficult to share that research with others.

As academics, we like to share our work with others. We realized we did not want to invest in proprietary architectures. Also, a lot of commercial products are not that good. There was a quality problem and we thought we could do a lot better.

The response was overwhelming and very quickly it was getting too big for Berkeley and we started the RISC-V foundation. The goal of the foundation is to maintain the RISC-V ISA standard and we have grown to over 60 companies—including the biggest names like Qualcomm, Samsung, Microsoft, Western Digital, IBM and Google.

HETTINGA: From there, how did RISC-V lead to the creation of the SiFive organization?

ASANOVIC: At Berkeley we’ve done a great deal of research into RISC architecture, involving teams and activities. They did implementations, ported the compilers and Linux and got other operating systems up and running. Having a ‘critical mass’ of graduate students working on this project allowed people from outside to pick it up and do real work with it. It started off as an idea to have a consultancy activity around RISC-V. The co-founders—Andrew Waterman and Yunsup Lee—soon realized the opportunity and that’s why I also decided to get involved as a founder.

HETTINGA: This seems to be a very significant time in the semiconductor industry. How would you characterize where we’re at today?

ASANOVIC: The semiconductor industry is in this perfect storm where we see that Moore’s Law is ending and that new technologies and developments are getting more and more expensive. There are fewer and fewer companies capable of pulling off a new design and making money out of it. At the same time there is a growth in demand for custom chips. Everybody is talking about the Internet of Things and all those devices will need a processor—and that cannot be the same processor for all solutions. There will be a growth in silicon products, but that growth will be in many fragmented markets. The old semiconductor business model—having one design and selling many millions of it— doesn’t work anymore. That has worked with the traditional computer and mobile phone markets, but the future will see perhaps hundreds of designs in lower volumes.

With SiFive we try to figure out how this works. The traditional users of the chips are now becoming the new manufacturers. Google. Microsoft, Amazon and a lot of other companies will design and make their own chips—not to sell to others, but to use them in their own products. It will allow them to add capabilities that are not available in standard off-the-shelf chips.

Our mission is to find out if we can help smaller companies and startups to do custom silicon design and invent new products with new capabilities. We believe there is a lot of untapped innovation there. But the problem is the barrier to enter custom silicon design is too high and those great ideas do not become a product. Solving that problem is the goal of SiFive.

Photo 1

SiFive’s RISC-V Arduino board makes it easy for small companies to get started with new designs.

HETTINGA: Tell us about SiFive’s RISC-V Arduino reference design board.

ASANOVIC: Our business model is to do quick developments of new chipsets and help the client to get into production at very low costs. To enable that, we made an Arduino board (at the time of the interview the new Arduino Cinque was introduced / WH) that runs very fast. And by putting it into the Arduino format a lot of small design companies will see it and can use it for new designs. The interesting thing about this product is that it will take the focus from the board to the chip level. Not only the board is open source but the chip design is too. That can open up completely new perspectives for makers, start-up companies and medium-sized businesses. All the design files of the chip are open source are on Github. This is unique in the semiconductor business. With SiFive we want to get rid of the friction in the industry. We don’t have a costly structure with NDAs and lawyers. A lower cost structure will also mean lower costs for our clients. You can come and take the designs as they are and use them.

SiFive | www.sifive.com

DSP vs. RISC Processors (EE Tip #110)

There are a few fundamental differences between DSP and RISC processors. One difference has to do with arithmetic. In the analog domain, saturation, or clipping, isn’t recommended. But it generally comes with a design when, for example, an op-amp is driven high with an input signal. In the digital domain, saturation should be prevented because it causes distortion of the signal being analyzed. But some saturation is better than overflow or wrap-around. Generally speaking, a RISC processor will not saturate, but a DSP will. This is an important feature if you want to do signal processing.

Let’s take a look at an example. Consider a 16-bit processor working with unsigned numbers. The minimum value that can be represented is 0 (0x0000), and the maximum is 65535 (0xFFFF). Compute:

out = 2 × x

where x is an input value (or an intermediate value in a series of calculations). With a generic processor, you’re in trouble when x is greater than 32767.

If x = 33000 (0x80E8), the result is out = 66000 (0x101D0). Because this value can’t be represented with 16 bits, the out = 2 × x processor will truncate the value:

out = 2 × 333000 = 464(0x01D0)

From that point on, all the calculations will be off. On the other end, a DSP (or an arithmetic unit with saturation) will saturate the value to its maximum (or minimum) capability:

out = 2 × 333000 = 65535(0xFFFF)

In the first case, looking at out, it would be wrong to assume that x is a small value. With saturation, the out is still incorrect, although it accurately shows that the input is a large number. Trends in the signal can be tracked with saturation. If the saturation isn’t severe (affecting only a few samples), the signal might be demodulated correctly.

Generic RISC processors like the NXP (Philips) LPC2138 don’t have a saturation function, so it’s important to ensure that the input values or the size of the variable are scaled correctly to prevent overflow. This problem can be avoided with a thorough simulation process.—Circuit Cellar 190, Bernard Debbasch, “ARM-Based Modern Answering Machine,” 2006.

This piece originally appeared in Circuit Cellar 190, 2006.