3D Tool Strengthens Marriage of PCB Design with Mechanical Design

Cadence Design Systems has announced its Cadence Sigrity 2018 release, which includes new 3D capabilities that enable PCB design teams to accelerate design cycles while optimizing cost and performance. According to the company, a 3D design and 3D analysis environment integrating Sigrity tools with Cadence Allegro technology provides a more efficient and less error-prone solution than current alternatives using third-party modeling tools, saving days of design cycle time and reducing risk.

In addition, a new 3D Workbench methodology bridges the gap between the mechanical and electrical domains, allowing product development teams to analyze signals that cross multiple boards quickly and accurately.

Since many high-speed signals cross PCB boundaries, effective signal integrity analysis must encompass the signal source and destination die, as well as the intervening interconnect and return path including connectors, cables, sockets and other mechanical structures.

Traditional analysis techniques utilize a separate model for each piece of interconnect and cascade these models together in a circuit simulation tool, which can be an error-prone process due to the 3D nature of the transition from the PCB to the connector. In addition, since the 3D transition can make or break signal integrity, at very high speeds designers also want to optimize the transition from the connector to the PCB or the socket to the PCB.

According to the company, the Sigrity 2018 release enables designers to take a holistic view of their system, extending design and analysis beyond the package and board to also include connectors and cables. An integrated 3D design and 3D analysis environment lets PCB design teams optimize the high-speed interconnect of PCBs and IC packages in the Sigrity tool and automatically implement the optimized PCB and IC package interconnect in Allegro PCB, Allegro Package Designer or Allegro SiP Layout without the need to redraw.
Until now, this has been an error-prone, manual effort requiring careful validation. By automating this process, the Sigrity 2018 release reduces risk, saves designers hours of re-drawing and re-editing and can save days of design cycle time by eliminating editing errors not found until the prototype reaches the lab. This reduces prototype iterations and potentially saves hundreds of thousands of dollars by avoiding re-spins and schedule delays.

A new 3D Workbench utility available with the Sigrity 2018 release bridges the mechanical components and the electronic design of PCB and IC packages, allowing connectors, cables, sockets and the PCB breakout to be modeled as one with no double counting of any of the routing on the board. Interconnect models are divided at a point where the signals are more 2D in nature and predictable. By allowing 3D extraction to be performed only when needed and fast, accurate 2D hybrid-solver extraction to be performed on the remaining structures before all the interconnect models are stitched back together, full end-to-end channel analysis can be performed efficiently and accurately of signals crossing multiple boards.

In addition, the Sigrity 2018 release offers Rigid-Flex support for field solvers such as the Sigrity PowerSI technology, enabling robust analysis of high-speed signals that pass from rigid PCB materials to flexible materials. Design teams developing Rigid-Flex designs can now use the same techniques previously used only on rigid PCB designs, creating continuity in analysis practices while PCB manufacturing and material processes continue to evolve.

Cadence | www.cadence.com

Tool Environment Upgrade Boosts Efficiency of Multi-Board PCB Designs

The latest release of Zuken’s system-level PCB design environment, CR-8000, includes several enhancements aimed at ensuring performance, quality and manufacturability. The CR-8000 family of applications spans the complete PCB engineering lifecycle: from system level planning through implementation and design for manufacturability. The CR-8000 environment also supports 3D IC packaging and chip/package/board co-design.

The focus of CR-8000 2018 is on enabling efficient front-loading of design constraints and specifications to the design creation process, coupled with sophisticated placement and routing capabilities for physical layout. This will increase efficiency and ensure quality through streamlined collaboration across the PCB design chain.
Front-loading of design intent from Design Gateway to Design Force has been achieved by adding an enhanced, unified constraint browser for both applications. This enables hardware engineers to assign topology templates, modify differential signals and assign clearance classes to individual signals. Using a rule stack editor during the circuit design phase, hardware engineers can now load design rules that include differential pair routing and routing width stacks directly from the design rule library into their schematic. Here they can modify and assign selected rules for improved cross talk and differential pair control. Finally, an enhanced component browser enables component variants to be managed in the schematic, and assigned in a user-friendly table.

Manual routing is supported by a new auto complete & route function that layout designers can use to complete manually routed traces in an automated way. Designers also have the option to look for paths on different layers while automatically inserting vias.

A new bus routing function allows layout designers to sketch paths for multiple nets to be routed over dense areas. An added benefit is the routing of individual signals to the correct signal length as per the hardware engineer’s front loaded constraints, to meet timing skew and budgets. If modifications to fully placed and routed boards are required, an automatic re-route function allows connected component pins to remain connected with a simple reroute operation during the move process. In all operations, clearance and signal length specifications are automatically controlled and adjusted by powerful algorithms.

To address manufacturing requirements for high-speed design, the automatic stitching of vias in poured conductive areas can be specified in comprehensive detail, for example, inside area online, perimeter outline or both inside and perimeter. Design-for-manufacturing (DFM) has been enhanced to include checks for non-conductor items, such as silkscreen and assembly drawing placed reference designators. A design rule check will make sure component reference designators are listed in the same order as the parts for visual inspection accuracy.

As many product engineers do not work with EDA tools, intelligent PDF documentation is required, especially in 3D. Design Force now supports creation of PRC files commonly used for 3D printing. The PRC files can be opened in PDF authoring applications such as Adobe Acrobat, where they are realized as a 3D PDF file complete with 3D models and bookmarks to browse the design.

Zuken Americas | us.zuken.com

Altium Sponsors 7 Teams at SpaceX Design Competition

Altium has announced that it sponsored seven teams at SpaceX’s 2018 Hyperloop Pod Competition, which took place on July 22 at SpaceX’s headquarters in Hawthorne, CA. The competition aims to accelerate the development of functional prototypes and encourage up-and-coming university and innovator teams to design and build the best transport Pod for high speed ground transportation. Altium has been a sponsor since the announcement of the first competition.

Elon Musk with the Warr Hyperloop Team

SpaceX held its first-ever Hyperloop Pod Competition in 2017 to give global teams the opportunity to design and build a Hyperloop Pod to bring to life Elon Musk’s vision of a high-speed ground transportation. Last year’s winner, WARR Hyperloop of Technical University of Munich (currently sponsored by Altium), reached a pod speed of 201 mph. This year’s competition was judged solely on one criterion: maximum speed with successful deceleration (without crashing). Additionally, all Pods must be self-propelled. Since its inception, the competition has continued to inspire electrical engineering students around the world to push the boundaries of innovation.

Altium plays an important role in these competitions by providing teams with the professional software they need to design circuit boards that allow the Pods to function. This past year, Altium’s sponsored team, Badgerloop, used Altium Designer to design boards like the STMicro nucleo microcontroller board and shield that they could reuse as new iterations of pods were developed. To streamline the workflow, they developed a subversion network which allowed them to work closely and collaboratively on PCB designs during the summer when team members resided across two continents and three time zones.

Altium is sponsoring seven teams who are attending the 2018 Hyperloop Pod Competition. The teams hail across five countries in the U.S., The Netherlands, Switzerland, Germany and Scotland. The teams include Delft Hyperloop of Delft University of Technology; HyperXite of University of California, Irvine; Swissloop of ETH Zurich; WARR Hyperloop of Technical University of Munich; UW Hyperloop of University of Washington; Badgerloop of University of Wisconsin–Madison and HYPED of University of Edinburgh.

Altium | www.altium.com

Siemens Acquires Austemper Design Systems

Siemens has entered into an agreement to acquire Austin, Texas-based Austemper Design Systems, a startup software company that offers analysis, auto-correction and simulation technology. This technology allows customers to test and harden IC designs for functional safety in applications such as automotive, industrial and aerospace systems. These are systems where functional safety and high reliability are mandatory for compliance to safety standards like ISO 26262.

ICs in these applications require three types of functional safety verification: for systemic faults, malicious faults and random hardware faults. Mentor’s existing Questa software (shown) is a leading technology for functional verification of systemic faults and provides solutions for verification of malicious faults for IC security. The software technology from Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults. This is expected to complement Mentor’s existing functional safety offerings including its Tessent product suite and Veloce platform.

Design teams at leading semiconductor and IP companies use Austemper’s innovative technology to analyze the registered-transfer level (RTL) code versions of their designs for faults and vulnerabilities. It can automatically correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is hardened and no longer susceptible to errors. Moreover, the Austemper technology performs simulation at orders of magnitude faster than competing solutions.

Siemens will integrate Austemper’s technology into Mentor’s IC verification portfolio as part of Siemens’ larger digitalization strategy, leveraging Siemens’ world-wide sales channel to make this functional safety solution available to companies developing digital twins of safety-critical systems at the heart of autonomous vehicles, smart cities and industrial equipment in Factory 4.0.

Mentor, A Siemens Business | www.mentor.com

EMC Analysis During PCB Layout

Catch Issues Earlier

If your electronic product design fails EMC compliance testing for its target market, that product can’t be sold. That’s why EMC analysis is such an important step. In this article, Craig shows how implementing EMC analysis during the design phase provides an opportunity to avoid failing EMC compliance testing after fabrication.

By Craig Armenti,
Mentor, A Siemens Business

Electromagnetic Compatibility (EMC) is generally defined as the ability of a product to function in its environment without introducing electromagnetic disturbance. EMC compliance is a necessary condition for releasing products to market. Simply stated, if a product does not pass EMC compliance testing for the target market, the product cannot be sold. Regulatory bodies around the world define limits on the radiated and conducted emissions that a device is allowed to produce. Automotive and aerospace manufacturers can set even stricter standards for their suppliers. Design teams are well aware of the importance of ensuring their product is EMC compliant. All that said, many do not attempt to perform EMC analysis during design.

There is a perception that EMC analysis during PCB layout can be a time-consuming task that is challenging to set up and properly configure, with difficult-to-interpret results. Historically, the focus of analysis during design has been on Signal Integrity (SI) and Power Integrity (PI). Manual EMC “analysis” typically is performed post-fabrication, based on the results of testing the actual product. What is often overlooked is that implementing EMC analysis during the design phase provides an opportunity to avoid failing EMC compliance testing after fabrication.

Figure 1
EMC analysis implemented during PCB layout

The current generation of ECAD tools offers EMC analysis functionality that is easy to use, with well-documented rule checks that often include an explanation for each principle and advice on how to address issues. Implementing EMC analysis at appropriate points during PCB layout, prior to fabrication, can mitigate the need for redesign(s) that affect both product development cost and overall time to market (Figure 1).

EMC Simplified

EMC can be a confusing topic, especially for new engineers and designers or those not well versed in the subject matter. Furthermore, there is often confusion as to the difference between electromagnetic compatibility (EMC) and electromagnetic interference (EMI). Although this article is not intended to be an in-depth tutorial on EMC and EMI theory, a quick review of the definitions is appropriate.
As previously stated, EMC is generally defined as the ability of a product to function in its environment without introducing electromagnetic disturbance. Specifically, the product must:

• Tolerate a stated degree of interference
• Not generate more than a stated amount of interference
• Be self-compatible

EMI is generally defined as disturbance that affects an electrical circuit, due to either electromagnetic induction or electromagnetic radiation.

To further simplify the two definitions: EMC is how vulnerable the product is to the environment, and EMI is what the product introduces into the environment (Figure 2).

Figure 2
The four basic EMC/EMI coupling mechanisms relative to the source and victim

The complexity of the topic contributes to the perception that implementing EMC analysis during PCB layout can be a time-consuming task that is challenging to set up and properly configure, with results that are difficult to interpret. The alternative, however, foregoing automated in-design analysis and waiting to test the actual product post-fabrication, has the potential to be significantly more time consuming and costly. Although EMC test labs are not required to provide the average EMC testing pass rate, several studies suggest that the first time pass rate is approximately 50%. Furthermore, EMC compliance failure has been cited as the second cause for redesigns in the automotive industry. Given that an EMC failure will require one or more redesigns that affect both product development costs and overall time to market, performing EMC analysis during PCB layout (designing for EMC compliance) is essential.

Left-Shift to Layout

The term “left-shift” within the engineering space is often used to describe the act of moving (or shifting) a task that would normally occur toward a later phase of the design process, to occur also during an earlier phase. . …

Read the full article in the July 336 issue of Circuit Cellar

Mentor | www.mentor.com

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Here’s a sneak preview of July 2018 Circuit Cellar:

TECHNOLOGIES FOR THE INTERNET-OF-THINGS

Wireless Standards and Solutions for IoT  
One of the critical enabling technologies making the Internet-of-Things possible is the set of well-established wireless standards that allow movement of data to and from low-power edge devices. Here, Circuit Cellar’s Editor-in-Chief, Jeff Child, looks at key wireless standards and solutions playing a role in IoT.

Product Focus: IoT Device Modules
The rapidly growing IoT phenomenon is driving demand for highly integrated modules designed to interface with IoT devices. This Product Focus section updates readers on this technology trend and provides a product album of representative IoT interface modules.

TOOLS AND TECHNIQUES AT THE DESIGN PHASE

EMC Analysis During PCB Layout
If your electronic product design fails EMC compliance testing for its target market, that product can’t be sold. That’s why EMC analysis is such an important step. In his article, Mentor Graphics’ Craig Armenti shows how implementing EMC analysis during the design phase provides an opportunity to avoid failing EMC compliance testing after fabrication.

Extreme Low-Power Design
Wearable consumer devices, IoT sensors and handheld systems are just a few of the applications that strive for extreme low-power consumption. Beyond just battery-driven designs, today’s system developers want no-battery solutions and even energy harvesting. Circuit Cellar’s Editor-in-Chief, Jeff Child, dives into the latest technology trends and product developments in extreme low power.

Op Amp Design Techniques
Op amps can play useful roles in circuit designs linking the real analog world to microcontrollers. Stuart Ball shares techniques for using op amps and related devices like comparators to optimize your designs and improve precision.

Wire Wrapping Revisited
Wire wrapping may seem old fashioned, but this tried and true technology can solve some tricky problems that arise when you try to interconnect different kinds of modules like Arduino, Raspberry Pi and so on. Wolfgang Matthes steps through how to best employ wire wrapping for this purpose and provides application examples.

DEEP DIVES ON MOTOR CONTROL AND MONITORING

BLDC Fan Current
Today’s small fans and blowers depend on brushless DC (BLDC) motor technology for their operation. In this article, Ed Nisley explains how these seemingly simple devices are actually quite complex when you measure them in action. He makes some measurements on the motor inside a tangential blower and explores how the data relates to the basic physics of moving air.

Electronic Speed Control (Part 1)
An Electronic Speed Controller (ESC) is an important device in motor control designs, especially in the world of radio-controlled (RC) model vehicles. In Part 1, Jeff Bachiochi lays the groundwork by discussing the evolution of brushed motors to brushless motors. He then explores in detail the role ESC devices play in RC vehicle motors.

MCU-Based Motor Condition Monitoring
Thanks to advances in microcontrollers and sensors, it’s now possible to electronically monitor aspects of a motor’s condition, like current consumption, pressure and vibration. In this article, Texas Instrument’s Amit Ashara steps through how to best use the resources on an MCU to preform condition monitoring on motors. He looks at the signal chain, connectivity issues and A-D conversion.

AND MORE FROM OUR EXPERT COLUMNISTS

Verifying Code Readout Protection Claims
How do you verify the security of microcontrollers? MCU manufacturers often make big claims, but sometimes it is in your best interest to verify them yourself. In this article, Colin O’Flynn discusses a few threats against code readout and looks at verifying some of those claimed levels.

Thermoelectric Cooling (Part 1)
When his thermoelectric water color died prematurely, George Novacek was curious whether it was a defective unit or a design problem. With that in mind, he decided to create a test chamber using some electronics combined with components salvaged from the water cooler. His tests provide some interesting insights into thermoelectric cooling.