HyperBus Interface Incorporated into JEDEC xSPI Standard

Cypress Semiconductor has announced the inclusion of Cypress’ high-bandwidth HyperBus 8-bit serial memory interface into the new eXpanded SPI (xSPI) electrical interface standard from the JEDEC Solid State Technology Association. The xSPI standard defines requirements for the compatibility of high-performance x8 serial interfaces, enabling controller and chipset manufacturers to design a universal memory controller. The inclusion of the HyperBus interface in the JEDEC xSPI standard simplifies designing in HyperBus-based memories and provides more flexibility to system designers to implement instant-on functionality in automotive, industrial and IoT applications.

According to Cypress, the company was the first NOR flash memory supplier to identify the market requirement for a high-speed, 8-bit bus and introduced the HyperBus interface in 2014, ushering in a new class of high-performance NOR flash and RAM solutions that enable instant-on functionality for autonomous driving and industry 4.0 applications. Cypress’ HyperBus-based memories include high-density HyperFlash NOR Flash devices with the bandwidth required for the highest-performance embedded systems and high-speed HyperRAM self-refresh DRAM devices for systems requiring expanded scratchpad memory.

The xSPI standard defines requirements for the compatibility of high-performance x8 serial interfaces, including read and write commands, electrical characteristics, signaling protocols for command and data transfers, and a standard pin-out in a BGA footprint.
hyperbus diagram

The 12-pin Cypress HyperBus interface consists of an 8-pin address/data bus, a differential clock (2 signals), one chip select and a read data strobe for the controller, reducing the overall cost of a system. Memories based on the interface enable faster systems with quicker response times and rich user experiences. The HyperBus interface enables a wide range of high-performance applications, such as automotive instrument clusters, infotainment and navigation systems and factory automation systems.

Cypress Semiconductor | www.cypress.com

MCU Enables 3D Graphics in Car Displays

Cypress Semiconductor has announced a new series in its Traveo automotive microcontroller family with more memory to support a hybrid instrument cluster with 3D graphics and up to 6 traditional gauges, as well as a head-up display. The highly integrated, single-chip devices in the S6J32xEK series include an advanced 3D and 2.5D graphics engine and provide scalability with Cypress’ low-pin-count HyperBus memory interface. The series continues Cypress’ expansion of its broad automotive portfolio with differentiated system performance via its MCUs, wireless radios, capacitive-touch solutions, memories and Power Management ICs (PMICs).
Cypress Traveo Automotive MCUs 2017

The Traveo S6J32xEK series integrates up to 4MB of high-density embedded flash, 512 KB RAM and 2 MB of Video RAM, an ARM Cortex-R5 core at 240 MHz performance, a Low-Voltage Differential Signaling (LVDS) video output, a Low-Voltage Transistor-Transistor Logic (LVTTL) video output and a 6x stepper motor control. This combination enables the devices to serve as single-chip solutions to drive two displays. The devices have up to two 12-pin HyperBus memory interfaces that dramatically improve read and write performance of graphical data and other data or code.

A single HyperBus interface can be used to connect to two memories for Firmware Over-The-Air (FOTA) updates, which enable end-users to get software fixes and new features and applications for their vehicles on-the-go. The devices support all in-vehicle networking standards required for instrument clusters, including Controller Area Network-Flexible Data (CAN-FD) and Ethernet AVB. Additionally, the series provides robust security with integrated enhanced secure hardware extension (eSHE) support.

The Traveo S6J32xEK series include 50 channels of 12-bit Analog to Digital Converters (ADC), 12 channels of multi-function serial interfaces and I2S interfaces with an audio to output the complex, high-quality sounds required in today’s instrument clusters. The devices’ support for Ethernet AVB delivers increased bandwidth in multimedia applications and reduced programming time. The S6J32xEK series offers functional safety features to support Automotive Safety Integrity Level (ASIL) B, and the devices feature a wide ambient temperature range of -40˚C to +105˚C. The Traveo family is backed by a comprehensive tools and software ecosystem that simplifies system integration, including AUTOSAR MCAL 4.0.3 support.

The Traveo S6J32xEK series is sampling now and will be in production in the first quarter of 2018. The MCUs are available in a 208-pin and 216-pin thermally enhanced quad flat package (TEQFP).

Cypress Semiconductor | www.cypress.com

New SLC NAND Flash Memory Family for High-Security Apps

Cypress Semiconductor Corp. recently announced a high-endurance, 1-to-4-Gb Single-Level Cell (SLC) SecureNAND family that reduces system costs and improves system security. It does this by providing a single nonvolatile memory with integrated block protection features for a variety of high-security applications, such as point-of-sale systems and wearables.Cypress SecureNAND

The SecureNAND family includes 1-Gb S34SL01G2, 2-Gb S34SL02G2, and 4-Gb S34SL04G2 devices. You can configure each device with nonvolatile block protection to store protected boot code, system firmware, and applications. They provide 100,000 program/erase cycles to ensure more than five years of system life. Their operating voltage range is 2.7  to 3.6 V and they support the industrial temperature range of –40° to 85°C.

The currently sampling 1-Gb S34SL01G2, 2-Gb S34SL02G2, and 4-Gb S34SL04G2 SecureNAND devices are available in a 63-BGA package.

Source: Cypress Semiconductor

TRACE32 Supports Spansion HyperFlash Memory

Lauterbach recently announced its support for the Spansion HyperFlash Memory with the TRACE32 tools. HyperBus Interface was introduced by Spansion in 2014 as an improvement on today’s low pin count memory interfaces and has been broadly implemented by the system-on-chip (SoC) manufactures.trace32_Lauterbach

HyperFlash Memory is based on the HyperBus interface and provides the important characteristics such as low latency, high read throughput, and space efficiency. TRACE32 tools support the HyperFlash memory with the intuitive, fast, and flexible Flash Programming feature that also provides you with control of reading, displaying, and erasing the content of the flash memory. The content is displayed in a standard hex dump, which allows the contents to be checked quickly. The tool supports the pairing of HyperFlash memory with the HyperBus interface and also with the ordinary Quad SPI controller.

Source: Lauterbach

F-RAM Expands the Density Range of Energy-Efficient Nonvolatile RAMs

Cypress Semiconductor Corp. today introduced a family of 4Mb serial Ferroelectric Random Access Memories (F-RAMs), which are the industry’s highest density serial F-RAMs. The 4-Mb serial F-RAMs feature a 40-MHz SPI, a 2-to-3.6-V operating voltage range and are available in industry-standard, RoHS-compliant package options. All Cypress F-RAMs provide 100 trillion read/write cycle endurance with 10-year data retention at 85˚C and 151 years at 65˚C.Cypress 4Mb Serial F-RAM

Cypress F-RAMs are ideal solutions for applications requiring continuous and frequent high-speed reading and writing of data with absolute data security. The 4-Mb serial F-RAM family addresses mission-critical applications such as industrial controls and automation, industrial metering, multifunction printers, test and measurement equipment, and medical wearables.

The 4-Mb serial F-RAMs are currently sampling in industry-standard 8EIAJ and 8TDFN packages. Production expected in the fourth quarter of 2015.

Source: Cypress Semiconductor


New SQI Interface SuperFlash Memory Devices

Microchip Technology recently launched the SST26VF family of 3-V Serial Quad I/O interface (SQI interface) SuperFlash memory devices. Available with 16-, 32- or 64-Mb of memory, the “26 Series” family is manufactured using Microchip’s high-performance CMOS SuperFlash technology.

The SST26VF memory family provides fast erase times due to its use of SuperFlash technology. Sector and block erase commands are completed in just 18 ms, and a full chip erase operation is completed in 35 ms. Competitors’ devices require 10 to 20 s to complete a full chip erase operation, making the SST26VF approximately 400× faster. These fast erase times can provide a significant cost savings to customers, by minimizing the time required for testing and firmware updates, and therefore increasing their manufacturing throughput.Microchip SST26VF

Microchip’s SQI interface is a low pin count, high-speed 104 MHz quad-bit address and data multiplex I/O serial interface, which allows for high data throughput in a small package. This interface enables low-latency execute-in-place (XIP) capability with minimal processor buffer memory, reducing the overall design footprint compared to traditional parallel memory interfaces. The SST26VF family provides faster data throughput than a comparable x16 parallel flash device, without the associated high cost and high pin count of parallel flash. The SQI interface also offers full command-set backward compatibility for the ubiquitous SPI protocol.

Designed for low power consumption, the SST26VF is ideal for energy-efficient embedded systems. Standby current consumption is 15 µA (typical), and the active read current at 104 MHz is 15 mA (typical). The combination of 3-V operation with low power consumption and small-form-factor packaging makes the SST26VF devices an excellent choice for applications such as servers, printers, cloud computing systems, HDTV, Internet gateways, appliances, security systems, and a broad range of embedded systems.

The SST26VF devices also offer 100 years of data retention and device endurance of over 100,000 erase/write cycles. Enhanced safety features include software write protection of individual blocks for flexible data/code protection. In addition, the upper and lower 64 KB of memory are partitioned into smaller, 8-KB sectors that can both read- and write-lock. In addition, the devices include a One-Time Programmable (OTP) 2-KB Secure ID area, consisting of a 64-bit, factory-programmed unique ID and a user-programmable block. These features protect against unauthorized access and malicious read, program and erase intentions. The devices also include a JEDEC-compliant Serial Flash Discoverable Parameter (SFDP) table, which contains identifying information about the functions and capabilities of the SST26VF devices for simpler software design.

The three-member SST26VF family is available now for sampling and volume production in multiple package options, including eight-pin SOIC and SOIJ, 16-pin SOIC, eight-contact WDFN and 24-ball TBGA, as well as in die and wafer form. In 10,000-unit quantities, the 16-Mb SST26VF016B starts at $0.90 each, the 32-Mbit SST26VF032B starts at $1.17 each, and the 64-Mbit SST26VF064B starts at $1.84 each.

Source: Microchip Technology

Emerging Memory Technologies

Some experts predict it will be at least another decade before new memory technologies offer the low prices and wide availability to compete with NAND-based flash memory. Nonetheless, it’s worthwhile to look at potential NAND-flash successors, including phase-change RAM (PRAM), resistive RAM (ReRAM), and magnetoresistive RAM (MRAM).

In December’s Circuit Cellar magazine, now available online, Faiz Rahman describes and compares the newest memory technologies available for embedded systems.

“I cover only those devices that are now commercially available, but bear in mind that many other technologies are being hotly pursued in academic and corporate research labs worldwide,” says Rahman, an Ohio University visiting professor who received his PhD in Electrical Engineering from Imperial College, London.

For example, last summer MIT Technology Review reported on a startup company’s testing of crossbar memory. The new technology, according to an August 14, 2013, article written by Tom Simonite, can store data 40 times as densely as the most compact memory available and is faster and more energy-efficient.

Here are the commercially-available technologies Rahman considers and some of his insights. (For the full article with more details, including an update on manufacturers of the latest memory devices, check out the December issue.)

One of the most interesting memory types to emerge in recent years is one that stores data as order or disorder in small islands of a special material. The structural transition

The structure of phase-change RAM cells in reset and set states is shown.

The structure of phase-change RAM cells in reset and set states is shown.

between ordered and disordered phases is driven by controlled heating of the material island…

There have been several recent advances in phase-change RAM (PRAM) technology. Perhaps the most remarkable is the ability to control the cell-heating current precisely enough to create several intermediate cell-resistance values. This immediately increases the memory capacity as each cell can be made to store more than one bit. For example, if eight resistance values can be created and distinguished, then the cell can be used to store three bits, thus tripling the memory capacity. This is now a routinely used technique implemented with PRAM devices.

We have all wished for a computer with no start-up delay that could be ready to use almost as soon as it was powered up. Such a computer will need to use an inexpensive

A spin-torque magnetoresistive RAM cell’s structure includes a free layer, a tunnel barrier, and a fixed layer.

A spin-torque magnetoresistive RAM cell’s structure includes a free layer, a tunnel barrier, and a fixed layer.

but fast nonvolatile memory. This combination is difficult to come by, but proponents of magnetoresistive RAM (MRAM) think boot times could soon become outdated as this new memory becomes a mature product….

MRAM’s nonvolatility alone will not make it a potential game-changing technology. Its high-access speed is what makes it special. Unlike other nonvolatile memory (e.g., EEPROMs and flash), MRAM boasts typical access speeds of 35 ns and potentially as short as 4 ns, with further developments. This combined with MRAM’s extremely high endurance and data retention periods of more than 20 years even makes the technology suitable for use as CPU cache memories, which is a very demanding application.

One further advantage of MRAM is that its basic architecture—where the access transistor can be formed directly on top of the magnetic tunnel junction (MTJ)—enables very dense integration, greatly reducing the cost of storage per bit and making MRAM well suited for use in solid-state disks.

In many ways, DRAM is an example of an ideal memory, if it weren’t for its volatility… The problem is that the charge stored in a DRAM cell tends to disappear due to self-discharge

A ferroelectric RAM cell’s organizational structure is shown.

A ferroelectric RAM cell’s organizational structure is shown.

after only a few milliseconds. This means that all DRAM chips have to be periodically read and every cell’s state must be restored every few milliseconds. The requirement for periodic “refresh” operations increases the power consumption of DRAM banks, in addition to endangering data integrity in the case of even short power supply dips.

Within this backdrop, ferroelectric RAM (FRAM) became a potential game changer when it was introduced in the early 1990s…The permanence of induced electrical polarization in ferroelectric capacitors endows FRAMs with their nonvolatility. To write a particular bit, a FRAM’s cell capacitor is briefly charged in one direction to polarize the ferroelectric material between its plates. The capacitor voltage can then be removed and the bit state will be retained in the directional sense of the dielectric material’s polarization. No charges may leak away, and the polarization can be maintained for many years making FRAM, in a sense, a nonvolatile analog of DRAM….

A big advantage of using FRAM in microcontrollers is that just one memory can be used for program, data, and information storage instead of having to use separate flash, SRAM, and EEPROM blocks, which has been the trend so far.

Phase-change memory uses programmed heat-generating current pulses to affect memory cell resistance changes. However, resistive RAM (ReRAM)—a still developing memory breed—uses voltage pulses to make resistance changes. This memory technology

A typical resistive RAM cell’s structure is shown.

A typical resistive RAM cell’s structure is shown.

utilizes materials and structures where suitable voltages can alter memory cells’ resistive states so they can store one or more data bits, similar to PRAM.

There are strong hints that ReRAM is capable of very fast switching with symmetric read and write times of less than 10 ns. This comes with a remarkably low power consumption, which should make this technology ideal for many applications.

As if these attributes were not enough, ReRAM cells are very small and can be placed extremely close together, which results in high-density memory fabrics.

Rahman’s article also introduces manufacturers offering products with the latest memory technologies, but he declares no single memory device the best. Despite manufacturers extolling their particular products, those that succeed will need to be available in high volume and at low cost, he says. They also must offer high-storage densities, he says, a bar most new memory technologies struggle to reach.

Do Small-RAM Devices Have a Future? (CC 25th Anniversary Preview)

What does the future hold for small-RAM microcontrollers? Will there be any reason to put up with the constraints of parts that have little RAM, no floating point, and 8-bit registers? The answer matters to engineers who have spent years programming small-RAM MCUs. It also matters to designers who are hoping to keep their skills relevant as their careers progress in the 21st century.

In the upcoming Circuit Cellar 25th Anniversary Issue—which is slated for publication in early 2013—University of Utah professor John Regehr shares his thoughts on the future of small-RAM devices. He writes:

For the last several decades, the role of small-RAM microcontrollers has been clear: they are used to perform fixed (though sometimes very sophisticated) functionality in environments where cost, power consumption, and size need to be minimized. They exploit the low marginal cost of additional transistors to integrate volatile RAM, nonvolatile RAM, and numerous peripherals into the same package as the processor core, providing a huge amount of functionality in a small, cheap package. Something that is less clear is the future of small-RAM microcontrollers. The same fabrication economics that make it possible to put numerous peripherals on a single die also permit RAM to be added at little cost. This was brought home to me recently when I started using Raspberry Pi boards in my embedded software class at the University of Utah. These cost $25 to $35 and run a full-sized Linux distribution including GCC, X Windows, Python, and everything else—all on a system-on-chip with 256 MB of RAM that probably costs a few dollars in quantity.

We might ask: Given that it is already the case that a Raspberry Pi costs about the same as an Arduino board, in the future will there be any reason to put up with the constraints of an architecture like Atmel’s AVR, where we have little RAM, no floating point, and 8-bit registers? The answer matters to those of us who enjoy programming small-RAM MCUs and who have spent years fine-tuning our skills to do so. It also matters to those of us who hope to keep our skills relevant through the middle of the 21st century. Can we keep writing C code, or do we need to start learning Java, Python, and Haskell? Can we keep writing stand-alone “while (true)” loops, or will every little MCU support a pile of virtual machines, each with its own OS?

Long & Short Term

In the short term, it is clear that inertia will keep the small-RAM parts around, though increasingly they will be of the more compiler-friendly varieties, such as AVR and MSP430, as opposed to earlier instruction sets like Z80, HC11, and their descendants. But will small-RAM microcontrollers exist in the longer term (e.g., 25 or 50 years)? I’ll attempt to tackle this question by separately discussing the two things that make small-RAM parts attractive today: their low cost and their simplicity.

If we assume a cost model where packaging and soldering costs are fixed but the marginal cost of a transistor (not only in terms of fabrication, but also in terms of power consumption) continues to drop, then small-RAM parts will eventually disappear. In this case, several decades from now even the lowliest eight-pin package, costing a few pennies, will contain a massive amount of RAM and will be capable of running a code base containing billions of lines…

Circuit Cellar’s Circuit Cellar 25th Anniversary Issue will be available in early 2013. Stay tuned for more updates on the issue’s content.

Q&A: Hai (Helen) Li (Academic, Embedded System Researcher)

Helen Li came to the U.S. from China in 2000 to study for a PhD at Purdue University. Following graduation she worked for Intel, Qualcomm, and Seagate. After about five years of working in industry, she transitioned to academia by taking a position at the Polytechnic Institute of New York University, where she teaches courses such as circuit design (“Introduction to VLSI”), advanced computer architecture (“VLSI System and Architecture Design”), and system-level applications (“Real-Time Embedded System Design”).

Hai (Helen) Li

In a recent interview Li described her background and provided details about her research relating to spin-transfer torque RAM-based memory hierarchy and memristor-based computing architecture.

An abridged version of the interview follows.

NAN: What were some of your most notable experiences working for Intel, Qualcomm, and Seagate?

HELEN: The industrial working experience is very valuable to my whole career life. At Seagate, I led a design team on a test chip for emerging memory technologies. Communication and understanding between device engineers and design communities is extremely important. The joined effects from all the related disciplines (not just one particular area anymore) became necessary. The concept of cross layers (including device/circuit/architecture/system) cooptimization, and design continues in my research career.

NAN: In 2009, you transitioned from an engineering career to a career teaching electrical and computer engineering at the Polytechnic Institute of New York University (NYU). What prompted this change?

HELEN: After five years of working at various industrial companies on wireless communication, computer systems, and storage, I realized I am more interested in independent research and teaching. After careful consideration, I decided to return to an academic career and later joined the NYU faculty.

NAN: How long have you been teaching at the Polytechnic Institute of NYU? What courses do you currently teach and what do you enjoy most about teaching?

HELEN: I have been teaching at NYU-Poly since September 2009. My classes cover a wide range of computer engineering, from basic circuit design (“Introduction to VLSI”), to advanced computer architecture (“VLSI System and Architecture Design”), to system-level applications (“Real-Time Embedded System Design”).

Though I have been teaching at NYU-Poly, I will be taking a one-year leave of absence from fall 2012 to summer 2013. During this time, I will continue my research on very large-scale integration (VLSI) and computer engineering at University of Pittsburgh.

I enjoy the interaction and discussions with students. They are very smart and creative. Those discussions always inspire new ideas. I learn so much from students.

Helen and her students are working on developing a 16-Kb STT-RAM test chip.

NAN: You’ve received several grants from institutions including the National Science Foundation and the Air Force Research Lab to fund your embedded systems endeavors. Tell us a little about some of these research projects.

HELEN: The objective of the research for “CAREER: STT-RAM-based Memory Hierarchy and Management in Embedded Systems” is to develop an innovative spin-transfer torque random access memory (STT-RAM)-based memory hierarchy to meet the demands of modern embedded systems for low-power, fast-speed, and high-density on-chip data storage.

This research provides a comprehensive design package for efficiently integrating STT-RAM into modern embedded system designs and offers unparalleled performance and power advantages. System architects and circuit designers can be well bridged and educated by the research innovations. The developed techniques can be directly transferred to industry applications under close collaborations with several industry partners, and directly impact future embedded systems. The activities in the collaboration also include tutorials at the major conferences on the technical aspects of the projects and new course development.

The main goal of the research for “CSR: Small Collaborative Research: Cross-Layer Design Techniques for Robustness of the Next-Generation Nonvolatile Memories” is to develop design technologies that can alleviate the general robustness issues of next-generation nonvolatile memories (NVMs) while maintaining and even improving generic memory specifications (e.g., density, power, and performance). Comprehensive solutions are integrated from architecture, circuit, and device layers for the improvement on the density, cost, and reliability of emerging nonvolatile memories.

The broader impact of the research lies in revealing the importance of applying cross-layer design techniques to resolve the robustness issues of the next-generation NVMs and the attentions to the robust design context.

The research for “Memristor-Based Computing Architecture: Design Methodologies and Circuit Techniques” was inspired by memristors, which have recently attracted increased attention since the first real device was discovered by Hewlett-Packard Laboratories (HP Labs) in 2008. Their distinctive memristive characteristic creates great potentials in future computing system design. Our objective is to investigate process-variation aware memristor modeling, design methodology for memristor-based computing architecture, and exploitation of circuit techniques to improve reliability and density.

The scope of this effort is to build an integrated design environment for memristor-based computing architecture, which will provide memristor modeling and design flow to circuit and architecture designers. We will also develop and implement circuit techniques to achieve a more reliable and efficient system.

An electric car model controlled by programmable emerging memories is in the developmental stages.

NAN: What types of projects are you and your students currently working on?

HELEN: Our major efforts are on device modeling, circuit design techniques, and novel architectures for computer systems and embedded systems. We primarily focus on the potentials of emerging devices and leveraging their advantages. Two of our latest projects are a 16-Kb STT-RAM test chip and an electric car model controlled by programmable emerging memories.

The complete interview appears in Circuit Cellar 267 (October 2012).