PCB Design Tools Evolve to Next Level

More Smarts, Wider Scope

PCB design tools and methods continue to evolve as they race to keep pace with faster, highly integrated electronics. Automated, rules-based chip placement is getting more sophisticated and tools are addressing the broader picture of the PCB design process.

By Jeff Child

Diagnostic fter decades of evolving their PCB design tool software packages, the leading tool vendors have the basics of PCB design nailed down—auto-routing, complex layer support, schematic capture and so on. In recent years, these companies have continued to come up with new enhancements to their tool suites, addressing a myriad of issues related to not just the PCB design itself, but the whole process surrounding it.

With that in mind, even in the last sixth months, PCB tool vendors have added a whole host of new capabilities to their offerings. These include special reliability analysis capabilities, sophisticated design-for-test (DFT) tools, extended team collaboration support and more.

High-Speed Signal Validation

Exemplifying these trends, in February Mentor Graphics started shipping its HyperLynx solution that provides automated and intelligent channel extraction for serializer/deserializer (SerDes) interfaces. HyperLynx PCB simulation technology for high-performance designs provides an end-to-end fully automated SerDes channel validation solution. Today’s advanced electronics products require intelligent high-speed design tools to ensure that designs perform as intended. With signaling rates of
50 Gbps becoming commonplace, and protocols like Ethernet pushing 400 Gbps bandwidth, traditional methods are insufficient. This is crucial for industries that demand superior high-speed performance such as automotive, networking, data centers, telecom and IoT/cloud-based products.

SerDes applies to interfaces like PCI Express (PCIe) that are used anywhere high-bandwidth is required. The problem is today’s hardware engineers lack time to fully understand the detailed signal integrity requirements of these interface protocols and may have limited access to signal integrity (SI) and 3D EM experts for counsel. Mentor’s new HyperLynx release provides tool-embedded protocol-specific channel compliance. The company claims it’s the industry’s first fully automatic validation tool for PCB SerDes interfaces. This includes a 3D explorer feature for design and layout optimization of non-uniform structures like breakouts and vias.

Using the new HyperLynx release, hardware engineers can easily perform protocol-specific compliance checks. The tool provides embedded protocol expertise for PCIe Gen3/4, USB 3.1 and COM-based technology for Ethernet and Optical Implementers Forum (OIF). Engineers can easily perform equalization optimization (CTLE, FFE, DFE) based on protocol architecture and constraints. HyperLynx’s 3D Explorer feature provides channel structure design and pre-layout optimization. Template-based 3D structure synthesis can be used for differential pair, BGA breakouts, via configurations, series-blocking capacitors and more (Figure 1).

Figure 1
Using HyperLynx, a 3D area is automatically created based on the available return path.

This isn’t the first Mentor Graphics time came out with PCB design tools that address a new dimension of PCB design. In March 2017, the company released its Xpedition vibration and acceleration simulation product for PCB systems reliability and failure prediction. The Xpedition product augments mechanical analysis and physical testing by introducing virtual accelerated lifecycle testing much earlier in the design process. The tool lets you simulate during the design process to determine PCB reliability and reduce field failure rates. You can also detect components on the threshold of failure that would be missed during physical testing. Finally, you can analyze pin-level Von-Mises stress and deformation to determine failure probability and safety factors.

DFT Plugin Added

In its most recent enhancement to its PCB tools offering, in February Zuken announced that it teamed up with boundary scan tool vendor XJTAG to add a plugin that enhances Zuken’s CR-8000 PCB Design Suite with a design for test (DFT) capability. . …

Read the full article in the June 335 issue of Circuit Cellar

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Software Tool Aids STM32 MCU Programming

STMicroelectronics offers a new software tool, STM32CubeProgrammer, the provides device-programming and firmware upgrades for STM32 microcontrollers in a unified, multi-platform and user-configurable environment. Ready to run on Windows, Linux,or MacOS operating systems, the STM32CubeProgrammer can program the STM32 microcontroller’s on-chip Flash/RAM or external memories using various file formats. Further capabilities include whole-memory or sector erase and programming microcontroller option bytes. Users can also generate encrypted files for secure programming (Secure Firmware Install/Update) to authenticate production and protect intellectual property.

With this tool, users can program STM32 microcontrollers through the device’s SWD (Single-Wire Debug) or JTAG debugging ports, or the bootloader ports (such as UART and USB). Hence the STM32CubeProgrammer brings the individual capabilities of the ST Visual Programmer, DFUse Device Firmware Update tool, Flash Loader, and ST-Link utility together within the STM32Cube ecosystem. ST will extend the STM32CubeProgrammer’s capabilities by adding programming access via microcontroller I2C and CAN ports.

The STM32CubeProgrammer provides many opportunities to customize and configure features, using either the GUI or the command-line interface (CLI). Also, this all-in-one tool can be used in standalone mode or integrated and controlled from a custom application. Programming can be done manually or automated using scripts.

STMicroelectronics | www.st.com

DFT Plugin Added to Zuken Design Suite

Zuken  and XJTAG have entered into a partnership to enhance Zuken’s CR-8000 with a design for test (DFT) capability that will improve test coverage during schematic entry. The capability is based on XJTAG’s DFT Assistant, and will be available later this year as a free plugin for Zuken’s CR-8000 Design Gateway users. CR-8000 is a native 3D product-XJTAG-DFT-Assistant-768x435centric design platform for PCB-based systems. CR-8000 directly supports architecture design, concurrent multi-board PCB design, chip/package/board co-design and full 3D MCAD co-design. CR-8000 Design Gateway is Zuken’s platform for logical circuit design and verification.

Increasingly, PCBs are densely populated making it difficult to gain manufacturing test access to pins under many packages, such as ball grid arrays (BGAs). JTAG was designed to enable test access, so an optimized JTAG design can have a positive impact on ROI. Failure to optimize JTAG test coverage at an early design stage can increase manufacturing costs and possibly require a board re-design. XJTAG DFT Assistant will help to validate correct JTAG chain connectivity while displaying boundary scan access and coverage onto the schematic diagram through full integration with CR-8000 Design Gateway.

Zuken | www.us.zuken.com

Impedance Matching Matters (EE Tip #145)

RF designers, as well as more and more digital-oriented designers, are used to thinking about impedance matching. But it is very easy to forget it when you are designing a non-RF project. A non-matched circuit will generate power losses as well as nasty reflection phenomena. (Refer to my article, “TDR Experiments,” Circuit Cellar 225, 2009.)

Impedance matching must be managed at the schematic stage, for example, by adding provisional matching pads for all integrated antennas, which will enable you to correct a slightly mis-adapted antenna (see Figure 1).

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Impedance matching is also a PCB design issue. As rule of thumb, you can’t avoid impedance-matched tracks when you are working with frequencies higher than the speed of light divided by 10 times the board size. A typical 10-cm board would translate to a cutoff frequency of 300 MHz. A digital designer would then say: “Cool, my clock is only 100 MHz. No problem!” But a 100-MHz square-ware clock or digital signal means harmonic frequencies in the gigahertz range, so it would be wise to show some concern.

The problem could also happen with very slow clocks when you’re using fast devices. Do you want an example? Last year, one of my colleagues developed a complex system with plenty of large and fast FPGAs. These chips were programmed through a common JTAG link and we ended up with nasty problems on the JTAG bus. We still had issues even when we slowed down the JTAG speed to 100 kHz. So, it couldn’t have been an impedance matching problem, right? Wrong. It was. Simply because the JTAG is managed by the FPGA with the same ultra-fast logic cells that manage your fast logic so with stratospheric skew rates which translated into very fast transitions on the JTAG lines. This generated ringing due to improper impedance matching, so there were false transitions on the bus. Such a problem was easy to solve once we pinpointed it, but we lost some days in between.—Robert Lacoste, CC25, 2013


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