Impedance Matching Matters (EE Tip #145)

RF designers, as well as more and more digital-oriented designers, are used to thinking about impedance matching. But it is very easy to forget it when you are designing a non-RF project. A non-matched circuit will generate power losses as well as nasty reflection phenomena. (Refer to my article, “TDR Experiments,” Circuit Cellar 225, 2009.)

Impedance matching must be managed at the schematic stage, for example, by adding provisional matching pads for all integrated antennas, which will enable you to correct a slightly mis-adapted antenna (see Figure 1).

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Impedance matching is also a PCB design issue. As rule of thumb, you can’t avoid impedance-matched tracks when you are working with frequencies higher than the speed of light divided by 10 times the board size. A typical 10-cm board would translate to a cutoff frequency of 300 MHz. A digital designer would then say: “Cool, my clock is only 100 MHz. No problem!” But a 100-MHz square-ware clock or digital signal means harmonic frequencies in the gigahertz range, so it would be wise to show some concern.

The problem could also happen with very slow clocks when you’re using fast devices. Do you want an example? Last year, one of my colleagues developed a complex system with plenty of large and fast FPGAs. These chips were programmed through a common JTAG link and we ended up with nasty problems on the JTAG bus. We still had issues even when we slowed down the JTAG speed to 100 kHz. So, it couldn’t have been an impedance matching problem, right? Wrong. It was. Simply because the JTAG is managed by the FPGA with the same ultra-fast logic cells that manage your fast logic so with stratospheric skew rates which translated into very fast transitions on the JTAG lines. This generated ringing due to improper impedance matching, so there were false transitions on the bus. Such a problem was easy to solve once we pinpointed it, but we lost some days in between.—Robert Lacoste, CC25, 2013

 

A Wire Is an Inductor (EE Tip #126)

I’m confident you know that you should keep wires and PCB tracks as short as possible. But I’m also sure that you will underestimate this problem fairly frequently.

Remember that 1 cm of a 0.25-mm-wide PCB track is roughly equivalent to an inductance of 10 nH. If this 10 nH is paired with, say, a 10-pF capacitor, that gives a resonant frequency as low as 500 MHz, which is easily below the third or fifth harmonics of the clock frequencies commonly seen on modern high-speed digital boards. Similarly, a 1-cm-long track will jeopardize the performances of any RF system such as a 2.4-GHz transceiver. There is only one solution: keep tracks and wires as short as possible. If you can’t, then use impedance-matched tracks.

Remember this rule especially for the ground connections: any grounded pad of any part working in high frequencies should be directly connected by avia to the underlying ground plane. And this via must be as close as possible to the pad, not some millimeters away.

Just yesterday I did a design review of a customer’s RF PCB. A small 0402 inductance was grounded through a via that was 3 mm away. It was a bad idea because the inductance was as low as 1 nH. Those 3 mm changed its value completely.—Robert Lacoste, “Mixed-Signal Designs,” CC25:25th Anniversary Issue, 2013.