New CPU Core Boosts Performance for Renesas MCUs

Renesas Electronics has announced the development of its third-generation 32-bit RX CPU core, the RXv3. The RXv3 CPU core will be employed in Renesas’ new RX microcontroller families that begin rolling out at the end of 2018. The new MCUs are designed to address the real-time performance and enhanced stability required by motor control and industrial applications in next-generation smart factory, smart home and smart infrastructure equipment.

The RXv3 core boosts CPU core architecture performance with up to 5.8 CoreMark/MHz, as measured by EEMBC benchmarks, to deliver industry-leading performance, power efficiency and responsiveness. The RXv3 core is backwards compatible with the RXv2 and RXv1 CPU cores in Renesas’ current 32-bit RX MCU families. Binary compatibility using the same CPU core instruction sets ensures that applications written for the previous-generation RXv2 and RXv1 cores carry forward to the RXv3-based MCUs. Designers working with RXv3-based MCUs can also take advantage of the robust Renesas RX development ecosystem to develop their embedded systems.
The RX CPU core combines a design optimized for power efficiency and a fabrication process producing excellent performance. The new RXv3 CPU core is primarily a CISC (Complex Instruction Set Computer) architecture that offers significant advantages over the RISC (Reduced Instruction Set Computer) architecture in terms of code density. RXv3 utilizes a pipeline to deliver high instructions per cycle (IPC) performance comparable to RISC. The new RXv3 core builds on the proven RXv2 architecture with an enhanced pipeline, options for register bank save functions and double precision floating-point unit (FPU) capabilities to achieve high computing performance, along with power and code efficiency.

The enhanced RX core five-stage superscalar architecture enables the pipeline to execute more instructions simultaneously while maintaining excellent power efficiency. The RXv3 core will enable the first new RX600 MCUs to achieve 44.8 CoreMark/mA with an energy-saving cache design that reduces both access time and power consumption during on-chip flash memory reads, such as instruction fetch.

The RXv3 core achieves significantly faster interrupt response times with a new option for single-cycle register saves. Using dedicated instruction and a save register bank with up to 256 banks, designers can minimize the interrupt handling overhead required for embedded systems operating in real-time applications such as motor control. RTOS context switch time is up to 20 percent faster with the register bank save function.

The model-based development (MBD) approach has penetrated various application developments; it enables the DP-FPU to help reduce the effort of porting high precision control models to the MCU. Similar to the RXv2 core, the RXv3 core performs DSP/FPU operations and memory accesses simultaneously to substantially boost signal processing capabilities.

Renesas plans to start sampling shipments of RXv3-based MCUs before the end of Q4 2018.

Renesas Electronics |

Expanded 32-bit MCU Family with Integrated Floating Point Unit Series

Microchip Technology has launched a new series of its high-performance PIC32MZ family of 32-bit microcontrollers that features an integrated hardware floating point unit (FPU) for high performance and lower latency in intensive single and double-precision math applications. This new 48-member PIC32MZ EF series also offers a 12-bit, 18 MSPS analog-to-digital converter (ADC) for a wide array of high-speed, wide-bandwidth applications. Additionally, the PIC32MZ EF supports an extensive DSP instruction set. This combination of DSP instructions, a double-precision FPU and a high-speed ADC improves code density, decreases latency and accelerates performance in process-intensive applications.Microchip32MZ

The PIC32MZ EF series is powered by Imagination’s MIPS M-Class core at 200MHz/330 DMIPS and 3.28 CoreMarks/MHz, along with dual-panel, live-update flash memory (up to 2 MB), large RAM (512 KB), and the widest selection of connectivity peripherals in the entire PIC32 portfolio, including a 10/100 Ethernet MAC, Hi-Speed USB MAC/PHY, and dual CAN ports.

The PIC32MZ EF, in the LCCG configuration, can support up to a WQVGA display without the added cost of external graphics controllers. An optional, full-featured hardware crypto engine is also available with a random number generator for high-throughput data encryption/decryption and authentication (e.g., AES, 3DES, SHA, MD5, and HMAC).
Accelerating product cycles and rapidly evolving customer demands are increasing time-to-market pressures on designers. Microchip’s MPLAB Harmony Integrated Software Framework provides a modular, easy-to-use GUI-based development ecosystem that helps ease integration and reduces testing and speed adaptation.

The new PIC32MZ EF series is also supported by Microchip’s free MPLAB X Integrated Development Environment (IDE), within which Harmony operates, as well as the MPLAB XC32 Compilers. The MPLAB ICD 3 In-Circuit Debugger (part # DV164035, $199.95) and MPLAB REAL ICE In-Circuit Emulator System (part # DV244005, $499.98) are also available.

Four new PIC32MZ EF development tools are also available today. The complete, turn-key PIC32MZ Embedded Connectivity with FPU EF Starter Kit ($119); the PIC32MZ Embedded connectivity with Floating Point Unit and Crypto Starter Kit ($119); the PIC32MZ2048EF PIM Explorer 16 Plug In Module ($25); and the PIC32MZ EF Audio 144-pin PIM for Bluetooth Audio Development Kit ($25).

The 48 members of the PIC32MZ EF series are available for sampling and volume production. The crypto engine is integrated into 16 of the PIC32MZ EF MCUs, and there are 12 MCUs with 512 KB of flash memory, 24 MCUs with 1 MB of flash memory, and 12 MCUs with 2 MB of flash memory. Pricing starts at $5.48 each in 10,000-unit quantities.

Source: Microchip Technology