December Circuit Cellar: A Sneak Preview

The December issue of Circuit Cellar magazine is coming soon. Want a sneak peak? We’ve got a great selection of excellent embedded electronics articles for you.

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 Here’s a sneak preview of December Circuit Cellar:

MICROCONTROLLERS IN MOTION

Special Feature: Electronics for Wearable Devices
Circuit Cellar Chief Editor Jeff Child examines how today’s microcontrollers, sensors and power electronics enable today’s wearable products.

329 Cover Screen CapSimulating a Hammond Tonewheel Organ
(Part 2)

Brian Millier continues this two-part series about simulating the Hammond tonewheel organ using a microcontrollers and DACs. This time he examines a Leslie speaker emulation.

Money Sorting Machines (Part 1)
In this new article series, Jeff Bachiochi looks the science, mechanics and electronics that are key to sorting everything from coins to paper money. This month he discusses a project that uses microcontroller technology to sort coins.

Designing a Home Cleaning Robot (Part 1)
This four-part article series about building a home cleaning robot starts with Nishant Mittal discussing his motivations behind to his design concept, some market analysis and the materials needed.

SPECIAL SECTION: GRAPHICS AND VISION

Designing High Performance GUI
It’s critical to understand the types of performance problems a typical end-user might encounter and the performance metrics relevant to user interface (UI) design. Phil Brumby of Mentor’s Embedded Systems Division examines these and other important UI design challenges.

Building a Robotic Candy Sorter
Learn how a pair of Cornell graduates designed and constructed a robotic candy sort. It includes a three degree of freedom robot arm and a vision system using a Microchip PIC32 and Raspberry Pi module.

Raster Laser Projector Uses FPGA
Two Cornell graduates describe a raster laser projector they designed that’s able to project images in 320 x 240 in monochrome red. The laser’s brightness and mirrors positions are controlled by an FPGA and analog circuitry.

ELECTRICITY UNDER CONTROL

Technology Spotlight: Power-over-Ethernet Solutions
Power-over-Ethernet (PoE) enables the delivery of electric power alongside data on twisted pair Ethernet cabling. Chief Editor Jeff Child explores the latest chips, modules and other gear for building PoE systems.

Component Overstress
When an electronic component starts to work improperly, Two likely culprits are electrical overstress (EOS) and electrostatic discharge (ESD). In his article, George Novacek breaks down the important differences between the two and how to avoid their effects.

AND MORE FROM OUR EXPERT COLUMNISTS:

Writing the Proposal
In this conclusion to his “Building an Embedded Systems Consulting Company” article series, Bob Japenga takes a detailed look at how to craft a Statement of Work (SOW) that will lead to success and provide clarity for all stakeholders.

Information Theory in a Nutshell
Claude Shannon is credited as one of the pioneers of computer science thanks to his work on Information Theory, informing how data flows in electronic systems. In this article, Robert Lacoste provides a useful exploration of Information Theory in an easily digestible way.

Microsoft Real-time AI Project Leverages FPGAs

At Hot Chips 2017 Microsoft unveiled a new deep learning acceleration platform, codenamed Project Brainwave. The system performs real-time AI. Real-time here means the system processes requests as fast as it receives them, with ultra-low latency. Real-time AI is becoming increasingly important as cloud infrastructures process live data streams, whether they be search queries, videos, sensor streams, or interactions with users.

Hot-Chips-Stratix-10-board-1-

 

The Project Brainwave system is built with three main layers: a high-performance, distributed system architecture; a hardware DNN engine synthesized onto FPGAs; and a compiler and runtime for low-friction deployment of trained models. Project Brainwave leverages the massive FPGA infrastructure that Microsoft has been deploying over the past few years. By attaching high-performance FPGAs directly to Microsoft’s datacenter network, they can serve DNNs as hardware microservices, where a DNN can be mapped to a pool of remote FPGAs and called by a server with no software in the loop. This system architecture both reduces latency, since the CPU does not need to process incoming requests, and allows very high throughput, with the FPGA processing requests as fast as the network can stream them.

Project Brainwave uses a powerful “soft” DNN processing unit (or DPU), synthesized onto commercially available FPGAs.  A number of companies—both large companies and a slew of startups—are building hardened DPUs.  Although some of these chips have high peak performance, they must choose their operators and data types at design time, which limits their flexibility.  Project Brainwave takes a different approach, providing a design that scales across a range of data types, with the desired data type being a synthesis-time decision. The design combines both the ASIC digital signal processing blocks on the FPGAs and the synthesizable logic to provide a greater and more optimized number of functional units.  This approach exploits the FPGA’s flexibility in two ways.  First, the developers have defined highly customized, narrow-precision data types that increase performance without real losses in model accuracy.  Second, they can incorporate research innovations into the hardware platform quickly (typically a few weeks), which is essential in this fast-moving space.  As a result, the Microsoft team achieved performance comparable to – or greater than – many of these hard-coded DPU chips but are delivering the promised performance today. At Hot Chips, Project Brainwave was demonstrated using Intel’s new 14 nm Stratix 10 FPGA.

Project Brainwave incorporates a software stack designed to support the wide range of popular deep learning frameworks. They support Microsoft Cognitive Toolkit and Google’s Tensorflow, and plan to support many others. They have defined a graph-based intermediate representation, to which they convert models trained in the popular frameworks, and then compile down to their high-performance infrastructure.

Microsoft | www.microsoft.com

Don’t Miss Our Bonus Newsletter: FPGA Technologies

As you know, Circuit Cellar’s newsletter covers four key themes each month. But August is a special month with a 5th Tuesday! As result, tomorrow coming to your inbox with be a special bonus newsletter theme: FPGA Technologies. In tomorrow’s newsletter you’ll get news about the products and technologies trends in the FPGA market. FPGAs have sv_gs_diagramevolved to become complete system chips. Today’s FPGAs pack in levels of processing, I/O and memory on one chip that once required several ICs or boards.

Also: We’ve added Drawings for Free Stuff to our weekly newsletters. Make sure you’ve subscribed to the newsletter so you can participate.

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You’ll get your “FPGA Technology” themed newsletter issue tomorrow.

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Remember, our new enhanced weekly CC Newsletter will switch its theme each week, so look for these in upcoming weeks:

Analog & Power. This newsletter content zeros in on the latest developments in analog and power technologies including DC-DC converters, AD-DC converters, power supplies, op-amps, batteries, and more.

Microcontroller Watch. This newsletter keeps you up-to-date on latest microcontroller news. In this section, we examine the microcontrollers along with their associated tools and support products.

IoT Technology Focus. The Internet-of-Things (IoT) phenomenon is rich with opportunity. This newsletter tackles news and trends about the products and technologies needed to build IoT implementations and devices.

Embedded Boards. Embedded boards are critical building blocks around which system developers can build all manor of intelligent systems. The focus here is on both standard and non-standard embedded computer boards.