FPGA Partial Reconfiguration

Many field-programmable gate array (FPGA) design modules have parameters, such as particular clock and I/O drive settings, that can only be adjusted during implementation, not at runtime. However, being able to make such adjustments in an FPGA design during operation is convenient.

In Circuit Cellar’s June issue, columnist Colin O’Flynn addresses how to use partial reconfiguration (PR) to sidestep such restrictions. Using difference-based PR, you can adjust digital clock module (DCM) attributes, I/O drive strength, and even look-up-table (LUT) equations, he says. O’Flynn’s article describes how he used PR on a Xilinx Spartan-6 FPGA to solve a specific problem. The article excerpt below elaborates:

Perfect Timing
The digital clock module (DCM) in a Xilinx Spartan-6 FPGA has a variety of features, including the ability to add an adjustable phase shift onto an input clock.

There are two types of phase shifts: fixed and variable. A fixed shift can vary from approximately –360° to 360° in 1.4° steps. A variable shift enables shifting over a smaller range, which is approximately ±5 nS in 30-ps steps.

Note the actual range and step size varies considerably for different operating conditions. Hence the problem: the provided variable phase shift interface is only useful for small phase shifts; any major phase shift must be fixed at design time.

To demonstrate how PR can be used to fix the problem, I’ll generate a design that implements a DCM block and use PR to dynamically reconfigure the DCM.

Figure 1—The system’s general block diagram is shown. A digital clock module (DCM) block synthesizes a new clock from the system oscillator and then outputs the clock to an I/O pin. The internal configuration access port (ICAP) interface is used to load configuration data. The serial interface connects the ICAP interface to a computer via a first in, first out (FIFO) buffer.

Figure 1—The system’s general block diagram is shown. A digital clock module (DCM) block synthesizes a new clock from the system oscillator and then outputs the clock to an I/O pin. The internal configuration access port (ICAP) interface is used to load configuration data. The serial interface connects the ICAP interface to a computer via a first in, first out (FIFO) buffer.

Streaming Bits
I used Xilinx’s ISE design suite to generate a design (see Figure 1). I did the usual step of creating the entire FPGA bitstream, which could then be programmed into the FPGA. The FPGA bitstream is essentially a completely binary blob tells you nothing about your design. The “FPGA native circuit description (NCD)” file is one step above the FPGA bitstream. The NCD file contains a complete description of the design mapped to the blocks available in your specific chip with all the routing of signals between those blocks and useful net names.

The NCD file contains enough information for you to do some edits to the FPGA design. Then you can use the NCD file to generate a new binary blob (bitstream) for programming. A critical part of PR is understanding that when you download this new blob, you can only download the difference between the original file and the new file. This is known as “difference-based PR,” and it is the only type of PR I’ll be discussing.

So what’s in the bitstream? The bitstream actually contains several different commands sent to the FPGA device, which instructs the FPGA to load configuration information, tells it the address information where the data is going to be loaded, and finally sends the actual data to load. Given a bitstream file, you can actually parse this information out. I’ve posted a Python script on ProgrammableLogicInPractice.com that does this for the Spartan-6 device.

A frame is the smallest portion of an FPGA that can be configured. The frame’s size varies per device. (For the Spartan-6 I used in this article, it is 65 × 16-bit words, or 1,040 bits per frame.) You must reload the entire frame if anything inside it changes, which brings me to the first “gotcha.” When using PR, everything inside that “frame” will be reloaded (i.e., parts of your design that haven’t changed may become temporarily invalid because they share a configuration frame with the part of your design that has changed).

O’Flynn’s full article goes on to explain more about framing, troubleshooting challenges along the way, and completing the reconfiguration. The article is available in the June issue, now available for membership download or single-issue purchase.

To further assist readers, O’Flynn has posted more information on the website that complements his monthly Circuit Cellar column, including a video of his project running.

“You can also see an example of how I integrated PR into my open-source ChipWhisperer project, which uses PR to dynamically program a phase shift into the DCMs inside the FPGA,” he says.

Experimentation and Engineering

Frederic Vecoven is software engineer living in Luxembourg who enjoys experimenting with everything from his home’s central heating controller to FPGAs. He has been designing micrcontroller-based projects for more than a dozen years and is currently working on an EPROM emulator.—Nan Price, Associate Editor


NAN: What is your current occupation?

FREDERIC:: I am a software principal engineer at Oracle.

NAN: Your website Vecoven.com features projects involving capacitors, microcontrollers, and EEPROM and hardware emulators. Tell us a little about the projects and your design process.

vecovenFREDERIC: At work I design firmware for high-end servers. At home I like to design my own stuff, so I have full control and can create new devices and/or enhance existing ones. I work on various projects and I don’t find enough time to document all of them on the website. For example, I designed a controller for the central heating in my house, but never documented it (it’s too “custom”). I love retrocomputing, which is how my FreHD project started. This is a hard-drive emulator for TRS-80 computers.

My design process starts from an idea (I have too many, so I must carefully select one) then a lot of thinking about the future implementation (as always, designing something is about compromises). Once I have a clear view in my mind about how things should work, I start prototyping. If possible, I use a breadboard or I create a PCB. Sometimes I do a lot of simulation before starting the prototyping, as this will save a lot of time. However, that cannot be done for all projects.

NAN: How long have you been designing microcontroller-based systems?

FREDERIC: More than 15 years.

NAN: How did you become interested in technology?

FREDERIC: When I was 13 years old I fell in love with computers when I saw a TRS-80 model in high school. I am thankful to my parents, who gave me a computer one year later.
I went to college and got a master’s degree in computer science. But I wasn’t satisfied, so I studied some more years to get another master’s degree, this time in electrical engineering. The combination of software and hardware is really powerful. A few years later, I relocated to the San Francisco Bay Area, but I am back in Europe now.

NAN: Describe the first embedded system you designed. Where were you at the time? What did you learn from the experience?

FREDERIC: My first big experience with a real embedded system was when I was working for Sun Microsystems. My group was writing the firmware for the system controllers of the SunFire 3800-6900 line. The embedded system was a small SPARC CPU running Wind River Systems’s VxWorks and the firmware was almost entirely written in Java.

NAN: What was the last electronics design-related product you purchased and how did you use it?

FREDERIC: I bought some FPGAs recently. I haven’t released any project with it yet, it is still a work in progress. My hobby time is very limited.

My idea is to use a CPU core and enhance it with new instructions to enable the generation of real-time signals. FPGAs are very powerful in that area, where a microcontroller would spend most of its time processing interrupts.

NAN: Are you currently working on or planning any projects?


This is Frederic’s PWM prototype for his Roland Super JX synthesizer.

FREDERIC: Yes, I have rewritten the Roland JX-10/MKS-70 firmware from scratch because I wanted to add PWM waveforms. This quickly turned into a big project. Currently, the prototype setup involves a simulator running the “assigner” code on my laptop. The laptop sends the sound board commands in System Exclusive (SysEx) Musical Instrument Digital Interface (MIDI) messages, which go to a microcontroller that extracts the payload from the SysEx. The payload is then sent to the sound board, which believes it got its instructions directly from the assigner. The sound board (which runs its own microcontroller) uses an EPROM emulator connected over USB, so I can easily modify the assigner code (running in the simulator) or the sound board code (running in the EPROM emulator) without having to program any chip. Note that I didn’t have an EPROM emulator, so I designed mine.


This oscilloscope capture shows the generated PWM signal.

FREDERIC: The power of CPUs and GPUs are really exciting. You can pretty much do everything with software now (a 32-bit core costs less than $5).
On the other side, people don’t pay enough attention to optimization, so I am sad anytime I see poorly written code. I am also excited with all the tools and hardware available today for so little cost. That wasn’t the case in the past, so it opens door to students and hobbyists.

NAN: Last question. Let’s say you had a full year and a nice budget to work on any embedded design project you wanted. Call it your “dream project.” What would it be?

FREDERIC: I would love to do some robotic design, but I am not an expert in mechanics and I don’t have the tools (e.g., lathe, milling machine, etc.). That would fill the gap: hardware, software, and mechanics.

June Issue: Vehicle Tracking, Bit Banging, and More

Circuit Cellar’s June issue is now online, outlining DIY projects ranging from an automated real-time vehicle locator to a  GPS-oriented solar tracker and offering solid advice on bit banging, FPGA reconfiguration, customizing the Linux kernel, and more.

June issueA persistent problem typically sparks the invention of projects featured in our magazine. For example, when the campus at Penn State Erie, The Behrend College, had a growth spurt, the local transit authority provided a shuttle bus to help students who were rushing from class to class. But ridership was low because of the bus’ unpredictable schedule.

So a college engineering team constructed a mobile application to track the bus. That system inspired the cover of our June issue and complements its communications theme.

The three-part system consists of a user’s smartphone running a HTML5-compatible browser, a base station consisting of an XTend 900-MHz radio connected to a Raspberry Pi single-board computer, and a mobile tracker including a GPS receiver, a Microchip Technology PIC18F26K22 microcontroller, and an XTend module.

The Raspberry Pi runs a web server to handle requests from a user’s smartphone. The user then receives accurate bus arrival times.

Also aligning with June’s theme, we present an article about implementing serial data transmission through bit banging. You’ll gain a better understanding of how serial data is transmitted and received by a microprocessor’s hardware UART peripheral. You’ll also learn how bit banging can achieve serial communication in software, which is essential when your embedded system’s microprocessor lacks a built-in UART.

Recognizing a rapidly unfolding communications trend, this issue includes an inventor’s essay about how the presence of Bluetooth Low Energy (BLE) in the latest mobile devices is sparking a big boom in innovative hardware/sensor add-ons that use your smartphone or tablet as an interface. Other communications-related articles include Part 2 of a close look at radio-frequency identification (RFID). This month’s installment describes the front-end analog circuitry for the RFID base station of a secure door-entry project.

In addition, we offer articles about adjusting your FPGA design while it’s operating, modifying the Linux kernel to suit your hardware and software designs, tools and techniques to boost your power supply, digital data encoding in wireless systems, GPS orientation of a solar panel, and an interview with Quinn Dunki, an embedded applications consultant and hacker.

The June issue is available for membership download or single-issue purchase.

A Serene Workspace for Board Evaluation and Writing

 Elecronics engineer, entrepreneur, and author Jack Ganssle recently sent us information about his Finksburg, MD, workspace:

I’m in a very rural area and I value the quietness and the view out of the window over my desk. However, there are more farmers than engineers here so there’s not much of a high-tech community! I work out of the house and share an office with my wife, who handles all of my travel and administrative matters. My corner is both lab space and desk. Some of the equipment changes fairly rapidly as vendors send in gear for reviews and evaluation.


Ganssle’s desk is home to ever-changing equipment. His Agilent Technologies MSO-X-3054A mixed-signal oscilloscope is a mainstay.

The centerpiece, though, is my Agilent Technologies MSO-X-3054A mixed-signal oscilloscope. It’s 500 MHz, 4 GSps, and includes four analog channels and 16 digital channels, as well as a waveform generator and protocol analyzer. I capture a lot of oscilloscope traces for articles and talks, and the USB interface sure makes that easy. That’s pretty common on oscilloscopes, now, but being an old-timer I remember struggling with a Polaroid scope camera.

The oscilloscope’s waveform generator has somewhat slow (20-ns) rise time when making pulses, so the little circuit attached to it sharpens this to 700 ps, which is much more useful for my work. The photo shows a Siglent SDS1102CML oscilloscope on the bench that I’m currently evaluating. It’s amazing how much capability gets packed into these inexpensive instruments.

The place is actually packed with oscilloscopes and logic analyzers, but most are tucked away. I don’t know how many of those little USB oscilloscope/logic analyzers vendors have sent for reviews. I’m partial to bench instruments, but do like the fact that the USB instruments are typically quite cheap. Most have so-so analog performance but the digital sampling is generally great.

Only barely visible in the picture, under the bench there’s an oscilloscope from 1946 with a 2” CRT I got on eBay just for fun. It’s a piece of garbage with a very nonlinear timebase, but a lot of fun. The beam is aimed by moving a magnet around! Including the CRT there are only four tubes. Can you imagine making anything with just four transistors today?

The big signal generator is a Hewlett-Packward 8640B, one of the finest ever made with astonishing spectral purity and a 0.5-dB amplitude flatness across 0.5 MHz to 1 GHz. A couple of digital multimeters and a pair of power supplies are visible as well. The KORAD supply has a USB connection and a serviceable, if klunky, PC application that drives it. Sometimes an experiment needs a slowly changing voltage, which the KORAD manages pretty well.

They’re mostly packed away, but I have a ton of evaluation kits and development boards. A Xilinx MicroZed is shown on the bench. It’s is a very cool board that has a pair of Cortex-A9s plus FPGA fabric in a single chip.

I use IDEs and debuggers from, well, everyone: Microchip Technology, IAR Systems, Keil, Segger, you name it. These run on a variety of processors but, along with so many others, more and more I’m using Cortex-M series parts.

My usual lab work is either evaluating boards, products and instruments, or running experiments that turn into articles. It pains me to see so much engineering is done via superstition today. For example, people pick switch contact debounce times based on hearsay or smoke signals or something. Engineers need data, so I tested about 50 pairs of switches to determine what real bounce characteristics are. The results are on my website. Ditto for watchdog timers and other important issues embedded people deal with.

Ganssle notes that his other “bench” is his woodworking shop. To learn more about Ganssle, read our 2013 interview.

Real-Time Processing for PCIe Digitizers

Agilent U5303A PCIe 12bit High-Speed DigitizerThe U5303A digitizer and the U5340A FPGA development kit are recent enhancements to Agilent Technologies’s PCI Express (PCIe) high-speed digitizers. The U5303A and the U5340A FPGA add next-generation real-time peak detection functionalities to the PCIe devices.

The U5303A is a 12-bit PCIe digitizer with programmable on-board processing. It offers high performance in a small footprint, making it an ideal platform for many commercial, industrial, and aerospace and defense embedded systems. A data processing unit (DPU) based on the Xilinx Virtex-6 FPGA is at the heart of the U5303A. The DPU controls the module functionality, data flow, and real-time signal processing. This feature enables data reduction and storage to be carried out at the digitizer level, minimizing transfer volumes and accelerating analysis.

The U5340A FPGA development kit is designed to help companies and researchers protect their IP signal-processing algorithms. The FPGA kit enables integration of an advanced real-time signal processing algorithm within Agilent Technologies’s high-speed digitizers. The U5340A features high-speed medical imaging, analytical time-of-flight, lidar ranging, non-destructive testing, and a direct interface to digitizer hardware elements (e.g., the ADC, clock manager, and memory blocks). The FPGA kit includes a library of building blocks, from basic gates to dual-port RAM; a set of IP cores; and ready-to-use scripts that handle all aspects of the build flow.

Contact Agilent Technologies for pricing.

Agilent Technologies, Inc.