SDK for OpenCL Dev Flow

Altera Corp. has simplified a programmer’s ability to accelerate algorithms in FPGAs. The Altera SDK for OpenCL version 14.0 includes a programmer-familiar rapid prototyping design flow that enables users to prototype designs in minutes on an FPGA accelerator board. Altera, along with its board partners, further accelerate the development of FPGA-based applications by offering reference designs, reference platforms and FPGA development boards that are supported by Altera’s OpenCL solution. These reference platforms also streamline the development of custom FPGA accelerators to meet specific application requirements.

Altera is the only company to offer a publicly available, OpenCL conformant software development kit (SDK). The solution allows programmers to develop algorithms with the C-based OpenCL language and harness the performance and power efficiencies of FPGAs. A rapid prototyping design flow included in the Altera SDK for OpenCL version 14.0 allows OpenCL kernel code to be emulated, debugged, optimized, profiled and re-compiled to a hardware implementation in minutes. The re-compiled kernels can be tested and run on an FPGA immediately, saving programmers weeks of development time.

Altera and its board partners further simplify the experience of getting applications up and running using FPGA accelerators by offering a broad selection of Altera-developed reference platforms, reference designs and FPGA accelerator boards. Altera provides a variety of design examples that demonstrate how to describe applications in OpenCL, including OPRA FAST Parser for finance applications, JPEG decoder for big data applications and video downscaling for video applications.

Design teams that want to create custom solutions that feature a unique set of peripherals can create their own custom FPGA accelerators and save significant development time by using Altera-developed reference platforms. The reference platforms include an SoC platform for embedded applications, a high-performance computing (HPC) platform and a low-latency network enabled platform which utilizes IO Channels.

One notable enhancement is production support for I/O Channels that allow streaming data into and out of the FPGA as well as kernel channels allowing the result reuse from one kernel to another in a hardware pipeline for significantly higher performance and throughput with little to no host and memory interaction. Another enhancement is production support for single-chip SoC solutions (Cyclone V SoC and Arria V SoC), where the host is an embedded ARM core processor integrated in the FPGA accelerator.

Altera’s SDK for OpenCL allows programmers to take OpenCL code and rapidly exploit the massively parallel architecture of an FPGA. Programmers targeting FPGAs achieve higher performance at significantly lower power compared to alternative hardware architectures, such as GPUs and CPUs. On average, FPGAs deliver higher performance at one-fifth the power of a GPU. Altera’s OpenCL solutions are supported by third-party boards through the Altera Preferred Board Partner Program for OpenCL. Visit www.altera.com/opencl.

The Altera SDK for OpenCL is currently available for download on Altera’s website (www.altera.com/products/software/opencl/opencl-index.html). The annual software subscription for the SDK for OpenCL is $995 for a node-locked PC license. For additional information about the Altera Preferred Board Partner Program for OpenCL and its partner members, or to see a list of all supported boards and links to purchase, visit the OpenCL section on Altera’s website.

[Source: Altera Corp.]

Robotics, Hardware Interfacing, and Vintage Electronics

Gerry O’Brien, a Toronto-based robotics and electronics technician at R.O.V. Robotics, enjoys working on a variety of projects in his home lab. His projects are largely driven by his passion for electronics hardware interfacing.

Gerry’s background includes working at companies such as Allen-Vanguard Corp., which builds remotely operated vehicle (ROV) robots and unmanned ground vehicles (UGVs) for military and police bomb disposal units worldwide. “I was responsible for the production, repair, programming and calibration of the robot control consoles, VCU (vehicle control unit) and the wireless communication systems,” he says.

Gerry recently sent Circuit Cellar photos of his home-based electronics and robotics lab. (More images are available on his website.) This is how he describes the lab’s layout and equipment:

In my lab I have various designated areas with lab benches that I acquired from the closing of a local Nortel  R&D office over 10 years ago.

All of my electronics benches have ESD mats and ground wrist straps.  All of my testing gear, I have purchased on eBay over the years….

PCB flip rack

PCB flip-rack

To start, I have my “Electronics Interfacing Bench” with a PCB flip-rack , which allows me to Interface PCBs while they are powered (in-system testing). I am able to interface my Tektronix TLA715 logic analyzer and other various testing equipment to the boards under test. My logic analyzer currently has two  logic I/O modules that have 136 channels each. So combined, I have 272 channels for logic analysis. I also have a four-channel digital oscilloscope module to use with this machine. I can now expand this even further by interfacing my newly acquired expansion box, which allows me to interface many more modules to the logic analyzer mainframe.

Gerry's lab bench

Gerry’s lab bench

Gerry recently upgraded his  Tektronix logic analyzer with an expansion box.

Gerry recently upgraded his Tektronix logic analyzer with an expansion box.

Interface probes

Logic analyzer interface probes

I also have a soldering bench where I have all of my soldering gear, including a hot-air rework station and 90x dissecting microscope with a video interface.

Dissecting microscope with video interface

Dissecting microscope with video interface

My devoted robotics bench has several robotic arm units, Scorbot and CRS robots with their devoted controllers and pneumatic Interface control boards.

Robotics bench

Robotics bench and CRS robot

On my testing bench, I currently have an Agilent/HP 54610B 500-MHz oscilloscope with the GPIB to RS-232 adapter for image capturing. I also have an Advantest model R3131A 9 kHz to 3-GHz bandwidth spectrum analyzer, a Tektronix model AFG3021 function generator, HP/Agilent 34401A multimeter and an HP 4CH programmable power supply. For the HP power supply, I built a display panel with four separate voltage output LCD displays, so that I can monitor the voltages of all four outputs simultaneously. The stock monochrome LCD display on the HP unit itself is very small and dim and only shows one output at a time.

Anyhow, my current testing bench setup will allow me to perform various signal mapping and testing on chips with a large pin count, such as the older Altera MAX9000 208-pin CPLDs and many others that I enjoy working with.

The testing bench

The testing bench

And last but not least… I have my programming and interfacing bench devoted to VHDL programming, PCB Design, FPGA hardware programming (JTAG), memory programming (EEPROM  and flash memory), web design, and video editing.

Interfacing bench and "octo-display"

Interfacing bench and “octo-display”

I built a PC computer and by using  a separate graphics display cards, one being an older Matrols four-port SVGA display card; I was able to build a “octo-display” setup. It seamlessly shares eight monitors providing a total screen resolution size of 6,545 x 1,980 pixels.

If you care to see how my monitor mounting assembly was built, I have posted pictures of its construction here.

A passion for electronics interfacing drives Gerry’s work:

I love projects that involve hardware Interfacing.  My area of focus is on electronics hardware compared to software programming. Which is one of the reasons I have focused on VHDL programming (hardware description language) for FPGAs and CPLDs.

I leave the computer software programming of GUIs to others. I will usually team up with other hobbyists that have more of a Knack for the Software programming side of things.  They usually prefer to leave the electronics design and hardware production to someone else anyhow, so it is a mutual arrangement.

I love to design and build projects involving vintage Altera CPLDs and FPGAs such as the Altera MAX7000 and MAX9000 series of Altera components. Over the years, I have a managed to collect a large arsenal of vintage Altera programming hardware from the late ’80s and early ’90s.  Mainly for the Altera master programming unit (MPU) released by Altera in the early ’90s. I have been building up an arsenal of the programming adapters for this system. Certain models are very hard to find. Due to the rarity of this Altera programming system, I am currently working on designing my own custom adapter interface that will essentially allow me to connect any compatible Altera component to the system… without the need of the unique adapter. A custom made adapter essentially.  Not too complicated at all really, it’s just a lot of fun to build and then have the glory of trying out other components.

I love to design, build, and program FPGA projects using the VHDL hardware description language and also interface to external memory and sensors. I have a devoted website and YouTube channel where I post various hardware repair videos or instructional videos for many of my electronics projects. Each project has a devoted webpage where I post the instructional videos along with written procedures and other information relating to the project. Videos from “Robotic Arm Repair” to a “DIY SEGA Game Gear Flash Cartridge” project. I even have VHDL software tutorials.

The last project I shared on my website was a project to help students dive into a VHDL based VGA Pong game using the Altera DE1 development board.

 

FPGA Partial Reconfiguration

Many field-programmable gate array (FPGA) design modules have parameters, such as particular clock and I/O drive settings, that can only be adjusted during implementation, not at runtime. However, being able to make such adjustments in an FPGA design during operation is convenient.

In Circuit Cellar’s June issue, columnist Colin O’Flynn addresses how to use partial reconfiguration (PR) to sidestep such restrictions. Using difference-based PR, you can adjust digital clock module (DCM) attributes, I/O drive strength, and even look-up-table (LUT) equations, he says. O’Flynn’s article describes how he used PR on a Xilinx Spartan-6 FPGA to solve a specific problem. The article excerpt below elaborates:

Perfect Timing
The digital clock module (DCM) in a Xilinx Spartan-6 FPGA has a variety of features, including the ability to add an adjustable phase shift onto an input clock.

There are two types of phase shifts: fixed and variable. A fixed shift can vary from approximately –360° to 360° in 1.4° steps. A variable shift enables shifting over a smaller range, which is approximately ±5 nS in 30-ps steps.

Note the actual range and step size varies considerably for different operating conditions. Hence the problem: the provided variable phase shift interface is only useful for small phase shifts; any major phase shift must be fixed at design time.

To demonstrate how PR can be used to fix the problem, I’ll generate a design that implements a DCM block and use PR to dynamically reconfigure the DCM.

Figure 1—The system’s general block diagram is shown. A digital clock module (DCM) block synthesizes a new clock from the system oscillator and then outputs the clock to an I/O pin. The internal configuration access port (ICAP) interface is used to load configuration data. The serial interface connects the ICAP interface to a computer via a first in, first out (FIFO) buffer.

Figure 1—The system’s general block diagram is shown. A digital clock module (DCM) block synthesizes a new clock from the system oscillator and then outputs the clock to an I/O pin. The internal configuration access port (ICAP) interface is used to load configuration data. The serial interface connects the ICAP interface to a computer via a first in, first out (FIFO) buffer.

Streaming Bits
I used Xilinx’s ISE design suite to generate a design (see Figure 1). I did the usual step of creating the entire FPGA bitstream, which could then be programmed into the FPGA. The FPGA bitstream is essentially a completely binary blob tells you nothing about your design. The “FPGA native circuit description (NCD)” file is one step above the FPGA bitstream. The NCD file contains a complete description of the design mapped to the blocks available in your specific chip with all the routing of signals between those blocks and useful net names.

The NCD file contains enough information for you to do some edits to the FPGA design. Then you can use the NCD file to generate a new binary blob (bitstream) for programming. A critical part of PR is understanding that when you download this new blob, you can only download the difference between the original file and the new file. This is known as “difference-based PR,” and it is the only type of PR I’ll be discussing.

So what’s in the bitstream? The bitstream actually contains several different commands sent to the FPGA device, which instructs the FPGA to load configuration information, tells it the address information where the data is going to be loaded, and finally sends the actual data to load. Given a bitstream file, you can actually parse this information out. I’ve posted a Python script on ProgrammableLogicInPractice.com that does this for the Spartan-6 device.

A frame is the smallest portion of an FPGA that can be configured. The frame’s size varies per device. (For the Spartan-6 I used in this article, it is 65 × 16-bit words, or 1,040 bits per frame.) You must reload the entire frame if anything inside it changes, which brings me to the first “gotcha.” When using PR, everything inside that “frame” will be reloaded (i.e., parts of your design that haven’t changed may become temporarily invalid because they share a configuration frame with the part of your design that has changed).

O’Flynn’s full article goes on to explain more about framing, troubleshooting challenges along the way, and completing the reconfiguration. The article is available in the June issue, now available for membership download or single-issue purchase.

To further assist readers, O’Flynn has posted more information on the website that complements his monthly Circuit Cellar column, including a video of his project running.

“You can also see an example of how I integrated PR into my open-source ChipWhisperer project, which uses PR to dynamically program a phase shift into the DCMs inside the FPGA,” he says.

Experimentation and Engineering

Frederic Vecoven is software engineer living in Luxembourg who enjoys experimenting with everything from his home’s central heating controller to FPGAs. He has been designing micrcontroller-based projects for more than a dozen years and is currently working on an EPROM emulator.—Nan Price, Associate Editor

 

NAN: What is your current occupation?

FREDERIC:: I am a software principal engineer at Oracle.

NAN: Your website Vecoven.com features projects involving capacitors, microcontrollers, and EEPROM and hardware emulators. Tell us a little about the projects and your design process.

vecovenFREDERIC: At work I design firmware for high-end servers. At home I like to design my own stuff, so I have full control and can create new devices and/or enhance existing ones. I work on various projects and I don’t find enough time to document all of them on the website. For example, I designed a controller for the central heating in my house, but never documented it (it’s too “custom”). I love retrocomputing, which is how my FreHD project started. This is a hard-drive emulator for TRS-80 computers.

My design process starts from an idea (I have too many, so I must carefully select one) then a lot of thinking about the future implementation (as always, designing something is about compromises). Once I have a clear view in my mind about how things should work, I start prototyping. If possible, I use a breadboard or I create a PCB. Sometimes I do a lot of simulation before starting the prototyping, as this will save a lot of time. However, that cannot be done for all projects.

NAN: How long have you been designing microcontroller-based systems?

FREDERIC: More than 15 years.

NAN: How did you become interested in technology?

FREDERIC: When I was 13 years old I fell in love with computers when I saw a TRS-80 model in high school. I am thankful to my parents, who gave me a computer one year later.
I went to college and got a master’s degree in computer science. But I wasn’t satisfied, so I studied some more years to get another master’s degree, this time in electrical engineering. The combination of software and hardware is really powerful. A few years later, I relocated to the San Francisco Bay Area, but I am back in Europe now.

NAN: Describe the first embedded system you designed. Where were you at the time? What did you learn from the experience?

FREDERIC: My first big experience with a real embedded system was when I was working for Sun Microsystems. My group was writing the firmware for the system controllers of the SunFire 3800-6900 line. The embedded system was a small SPARC CPU running Wind River Systems’s VxWorks and the firmware was almost entirely written in Java.

NAN: What was the last electronics design-related product you purchased and how did you use it?

FREDERIC: I bought some FPGAs recently. I haven’t released any project with it yet, it is still a work in progress. My hobby time is very limited.

My idea is to use a CPU core and enhance it with new instructions to enable the generation of real-time signals. FPGAs are very powerful in that area, where a microcontroller would spend most of its time processing interrupts.

NAN: Are you currently working on or planning any projects?

Vecoven_PWM

This is Frederic’s PWM prototype for his Roland Super JX synthesizer.

FREDERIC: Yes, I have rewritten the Roland JX-10/MKS-70 firmware from scratch because I wanted to add PWM waveforms. This quickly turned into a big project. Currently, the prototype setup involves a simulator running the “assigner” code on my laptop. The laptop sends the sound board commands in System Exclusive (SysEx) Musical Instrument Digital Interface (MIDI) messages, which go to a microcontroller that extracts the payload from the SysEx. The payload is then sent to the sound board, which believes it got its instructions directly from the assigner. The sound board (which runs its own microcontroller) uses an EPROM emulator connected over USB, so I can easily modify the assigner code (running in the simulator) or the sound board code (running in the EPROM emulator) without having to program any chip. Note that I didn’t have an EPROM emulator, so I designed mine.

Vecoven_scope

This oscilloscope capture shows the generated PWM signal.

FREDERIC: The power of CPUs and GPUs are really exciting. You can pretty much do everything with software now (a 32-bit core costs less than $5).
On the other side, people don’t pay enough attention to optimization, so I am sad anytime I see poorly written code. I am also excited with all the tools and hardware available today for so little cost. That wasn’t the case in the past, so it opens door to students and hobbyists.

NAN: Last question. Let’s say you had a full year and a nice budget to work on any embedded design project you wanted. Call it your “dream project.” What would it be?

FREDERIC: I would love to do some robotic design, but I am not an expert in mechanics and I don’t have the tools (e.g., lathe, milling machine, etc.). That would fill the gap: hardware, software, and mechanics.

June Issue: Vehicle Tracking, Bit Banging, and More

Circuit Cellar’s June issue is now online, outlining DIY projects ranging from an automated real-time vehicle locator to a  GPS-oriented solar tracker and offering solid advice on bit banging, FPGA reconfiguration, customizing the Linux kernel, and more.

June issueA persistent problem typically sparks the invention of projects featured in our magazine. For example, when the campus at Penn State Erie, The Behrend College, had a growth spurt, the local transit authority provided a shuttle bus to help students who were rushing from class to class. But ridership was low because of the bus’ unpredictable schedule.

So a college engineering team constructed a mobile application to track the bus. That system inspired the cover of our June issue and complements its communications theme.

The three-part system consists of a user’s smartphone running a HTML5-compatible browser, a base station consisting of an XTend 900-MHz radio connected to a Raspberry Pi single-board computer, and a mobile tracker including a GPS receiver, a Microchip Technology PIC18F26K22 microcontroller, and an XTend module.

The Raspberry Pi runs a web server to handle requests from a user’s smartphone. The user then receives accurate bus arrival times.

Also aligning with June’s theme, we present an article about implementing serial data transmission through bit banging. You’ll gain a better understanding of how serial data is transmitted and received by a microprocessor’s hardware UART peripheral. You’ll also learn how bit banging can achieve serial communication in software, which is essential when your embedded system’s microprocessor lacks a built-in UART.

Recognizing a rapidly unfolding communications trend, this issue includes an inventor’s essay about how the presence of Bluetooth Low Energy (BLE) in the latest mobile devices is sparking a big boom in innovative hardware/sensor add-ons that use your smartphone or tablet as an interface. Other communications-related articles include Part 2 of a close look at radio-frequency identification (RFID). This month’s installment describes the front-end analog circuitry for the RFID base station of a secure door-entry project.

In addition, we offer articles about adjusting your FPGA design while it’s operating, modifying the Linux kernel to suit your hardware and software designs, tools and techniques to boost your power supply, digital data encoding in wireless systems, GPS orientation of a solar panel, and an interview with Quinn Dunki, an embedded applications consultant and hacker.

The June issue is available for membership download or single-issue purchase.