Low-Profile PCIe Board Platform

BittWare recently announced today its second low-profile PCIe board—the A5-PCIe-S (A5PS). The new board is based on Altera’s Arria V GZ FPGA, which provides a high level of system integration and flexibility for I/O, routing, and processing. Thus, the A5PS is a reliable platform for a variety of applications (e.g., network processing, security, broadcast, and signals intelligence).BittWare A5PS

Featuring dual SFP+ cages that run up to 12.5 Gbps, the A5PS provides dual 10GigE ports using optical transceivers as well as passive copper cabling up to 7 m. These ports are serviced by the advanced 28-nm Arria V GZ FPGA, which also supports a Gen3 x8 PCIe interface and either 8-GB DDR3 or 36-MB QDRII+. Sophisticated time-stamping and synchronization options are supported by dual SMA connectors for interfacing to 1-PPS or 10-MHz reference clocks, in addition to the tunable on-board high accuracy, temperature compensated oscillator (TCXO). A comprehensive Board Management Controller (BMC) with host software support for advanced system monitoring is also provided.

The A5PS features and specifications include:

  • Altera Arria V GZ FPGA
  • PCIe x8 interface supporting Gen1, Gen2, or Gen3
  • Dual SFP+ cages for 2x 10GigE: Support for a wide range of optical transceiver; built-in low-latency active drivers/receivers for passive copper cables up to 7 m
  • Memory options (pick one): DDR3 (single 72-bit bank of up to 8 GBytes DDR3-1600 with ECC); QDRII+ (two 18-bit banks of up to 144 Mb each—288 Mb or 36 MB total)
  • Board Management Controller for Intelligent Platform Management
  • USB 2.0 for programming, debug, or control
  • Timestamping and synchronization support
    • Dual SMA for reference clock/synchronization inputs
    • Tunable high-accuracy TCXO
    • Programmable clock synthesizer (Si5338)
  • Complete software support with BittWare’s BittWorks II Toolkit
  • Broad range of IP offerings
    • 10 GigE MAC
    • TCP/IP Offload Engines (TOE), UDP Offload Engines
    • PTP/IEEE-1588
    • PCIe DMA

The A5PS board currently costs $1,500 in 1000s for the A5PS with the Arria V GZ E1 with no external memory. Contact BittWare for additional configurations, pricing, and details.

Source: BittWare

 

RTG4 Radiation-Tolerant FPGAs for High-speed Signal Processing Applications

Microsemi Corp. today announced availability of its RTG4 high-speed, signal-processing radiation-tolerant FPGA family. The RTG4’s reprogrammable flash technology offers complete immunity to radiation-induced configuration upsets in the harshest radiation environments, requiring no configuration scrubbing, unlike SRAM FPGA technology. RTG4 supports space applications requiring up to 150,000 logic elements and up to 300 MHz of system performance.Microsemi RTG4-  3-4view

Typical uses for RTG4 include remote sensing space payloads, such as radar, imaging and spectrometry in civilian, scientific and commercial applications. These applications span across weather forecasting and climate research, land use, astronomy and astrophysics, planetary exploration, and earth sciences. Other applications include mobile satellite services (MSS) communication satellites, as well as high altitude aviation, medical electronics and civilian nuclear power plant control. Such applications have historically used expensive radiation-hardened ASICs, which force development programs to incur substantial cost and schedule risk. RTG4 allows programs to access the ease-of-use and flexibility of FPGAs without sacrificing reliability or performance.

The flexibility, reliability and performance of RTG4 FPGAs make it much easier to achieve this. RTG4 is Microsemi’s latest development in a long history of radiation-tolerant FPGAs that are found in many NASA and international space programs.

Key product features include:

  • Up to 150,000 logic elements; each includes a four-input combinatorial look-up table (LUT4) and a flip-flop with built-in single event upset (SEU) and single event transient (SET) mitigation
  • High system performance, up to 300 MHz
  • 24 serial transceivers, with operation from 1 Gbps to 3.125 Gbps
  • 16 SEU- and SET-protected SpaceWire clock and data recovery circuits
  • 462 SEU- and SET-protected multiply-accumulate mathblocks
  • More than 5 Mb of on-board SEU-protected SRAM
  • Single event latch-up (SEL) and configuration memory upset immunity
  • Total ionizing dose (TID) beyond 100 Krad

Engineering silicon, Libero SoC development software, and RTG4 development kits are available now. RTG4 FPGAs and development kits have already shipped to some of the 120+ customers engaged in the RTG4 lead customer program. Flight units qualified to MIL-STD-883 Class B are expected to be available in early 2016.

Microsemi will present more information on RTG4 FPGAs in a live webinar on May 6 and will also be hosting Microsemi Space Forum events in the U.S., India and Europe starting in June, presenting information on RTG4 FPGAs and the extensive range of Microsemi space products.

Source: Microsemi Corp.

SoC FPGA Development Kit for Audio & Processing Applications

Coveloz recently announced the availability of its Pro Audio Ethernet AVB FPGA Development Kit, which is a ready-to-play platform for building scalable, cost-effective networked audio and processing applications built on modular hardware.Covelozpro-audio-dev-kit

Coveloz introduced its Networked Pro Audio SoC FPGA Development Kit during the Integrated System Europe (ISE) show in Amsterdam. According to the company, the new platform will enable manufacturers to achieve faster AVnu certification for new AVB solutions, creating an ideal development environment for live sound, conferencing systems, public address, audio post production, music creation, automotive infotainment and ADAS applications.

At the heart of the Coveloz development platform is a highly integrated System-on-Module (SOM), featuring an Altera Cyclone V SoC FPGA, which includes a dual-core ARM A9 processor, DDR3 memory and a large FPGA fabric, all in a low cost and compact package. The kit includes a multitude of networking and audio interfaces, including three Gigabit Ethernet ports as well as I2S, AES10/MADI, AES3/EBU and TDM audio.

Coveloz provides FPGA and Linux firmware enabling designers to quickly build AVnu Certified products for the broadcast, pro-audio/video and automotive markets. The platform is aimed at time-synchronized networks and includes grandmaster, PPS and word clock inputs and outputs as well as high quality timing references.

The Coveloz development kit is also host to the BACH-SOC platform, which integrates AES67 and Ethernet AVB audio networking and processing. Both SoC and PCIe-based FPGA implementations are available.

The Coveloz Bach Module is a full-featured and programmable audio networking and processing solution for easily integrating industry-standard AES67 and/or Ethernet AVB/TSN networking into audio/video distribution and processing products. The solution enables products with over 128+128 channels of digital streaming and 32-bit audio processing at 48, 96, or 192 kHz.

Supporting a wide range of interfaces, Coveloz complements the development platform with a comprehensive software toolkit and engineering services to help manufacturers reducing time to market. Coveloz also provides application examples to demonstrate the capabilities of the BACH-SOC platform.

The programmable BACH-SOC can be customized to a particular application in many ways—for instance, from selecting the number and type of audio interface to choosing audio processing alone, transport alone, or a combination.

Source: Coveloz

Synchronous Buck Regulator with Output Tracking and Sequencing for FPGAs and Microprocessors

Intersil Corp. recently announced the availability of the ISL8002B synchronous buck (step-down) switching regulator, which delivers up to 2 A of continuous output current from a 2.7- to 5.5-V input supply. Its 2-MHz switching frequency provides superior transient response, and its key features—including programmable soft-start and output tracking and sequencing of FPGAs and microprocessors—increase system reliability for point-of load conversions in networking, factory automation, instrumentation, and medical equipment.Intersil ISL8002B

The ISL8002B enables greater system reliability through several innovative features. For example, the regulator’s output tracking and sequencing of FPGAs and MPUs ensures sensitive multi-rails properly start up and shutdown. In addition, its output rails are configurable for coincidental, ratio metric, or sequential settings, ensuring the FPGA or MPU’s internal ESD diodes are not biased or overstressed during rising or falling outputs. The ISL8002B’s undervoltage lockout and several other protection/stability features protect the system from damage from unwanted electrical fault events. And its unique negative current protection prevents switch failure.

The ISL8002B’s superior transient response and high level of integration enable a complete synchronous step-down DC/DC converter solution in less than a 0.10 in2 footprint. By integrating low RDS(ON) high-side PMOS and low-side NMOS MOSFETs, the buck regulator eliminates the need for a bootstrap capacitor and diode. Its high efficiency enables the use of small inductors to further reduce board space.

Features and specifications:

  • Dimensions: 2 mm × 2 mm
  • Output tracking and sequencing
  • Switching at high frequency, 2 MHz
  • High peak efficiency: up to 95%
  • Wide input voltage range: 2.7 to 5.5 V
  • Maximum output current: 2A
  • Under voltage lockout, overvoltage protection
  • Selectable PFM or PWM operation
  • Over current, short-circuit protection
  • Over temperature/thermal protection

The ISL8002B synchronous buck regulator is available in a 2 mm  × 2 mm, eight-pin TDFN package. It costs $1 in 1,000-piece quantities. The ISL8002B DEMO1Z demonstration board is available for $23.

Source: Intersil Corp.

 

 

Quad Channel DPWM Step-Down Controller

Exar Corp. has introduced the XR77128, a universal PMIC that drives up to four independently controlled external DrMOS power stages at currents greater than 40 A for the latest 64-bit ARM processors, FPGAs, DSPs and ASICs. DrMOS technology is quickly growing in popularity in telecom and networking applications. These same applications find value in Exar’s Programmable Power technology which allows low component count, rapid development, easy system integration, dynamic control and telemetry. Depending on output current requirements, each output can be independently configured to directly drive external MOSFETs or DrMOS power stages.EX045_XR77128

The XR77128 is quickly configured to power nearly any FPGA, SoC, or DSP system through the use of Exar’s design tool, PowerArchitect, and programmed through an I²C-based SMBus compliant serial interface. It can also monitor and dynamically control and configure the power system through the same I²C interface. Five configurable GPIOs allow for fast system integration for fault reporting and status or for sequencing control.  A new Arduino-based development platform allows software engineers to begin code development for telemetry and dynamic control long before their hardware is available.

The XR77128 is available in a RoHS-compliant, green/halogen free space-saving 7 mm × 7 mm TQFN. It costs $7.75 in 1000-piece quantities.

Source: Exar Corp.

Industry’s Smallest Dual 3A/Single 6A Step-Down Power Module

Intersil Corp. recently announced the ISL8203M, a dual 3A/single 6A step-down DC/DC power module that simplifies power supply design for FPGAs, ASICs, microprocessors, DSPs, and other point of load conversions in communications, test and measurement, and industrial systems. The module’s compact 9.0 mm × 6.5 mm × 1.83 mm footprint combined with industry-leading 95% efficiency provides power system designers with a high-performance, easy-to-use solution for low-power, low-voltage applications.INT0325_ISL8203M_Intersil_Power_Module The ISL8203M is a complete power system in an encapsulated module that includes a PWM controller, synchronous switching MOSFETs, inductors and passive components to build a power supply supporting an input voltage range of 2.85 to 6 V. With an adjustable output voltage between 0.8 and 5 V, you can use one device to build a single 6-A or dual output 3-A power supply.

Designed to maximize efficiency, the ISL8203M power module offers best-in-class 15° C/W thermal performance and delivers 6 A at 85°C without the need for heatsinks or a fan. The ISL8203M leverages Intersil’s patented technology and advanced packaging techniques to deliver high power density and the best thermal performance in the industry, allowing the ISL8203M to operate at full load over a wide temperature range. The power module also provides over-temperature, over-current and under-voltage lockout protection, further enhancing its robustness and reliability.

Features and specifications:
•       Dual 3-A or single 6-A switching power supply
•       High efficiency, up to 95°
•       Wide input voltage range: 2.85 to 6 V
•       Adjustable output range: 0.8 to 5 V
•       Internal digital soft-start: 1.5 ms
•       External synchronization up to 4 MHz
•       Overcurrent protection

The ISL8203M power module is available in a 9 mm × 6.5 mm, QFN package. It costs $5.97 in 1,000-piece quantities. The ISL8203MEVAL2Z evaluation costs $67.

Source: Intersil

Impedance Matching Matters (EE Tip #145)

RF designers, as well as more and more digital-oriented designers, are used to thinking about impedance matching. But it is very easy to forget it when you are designing a non-RF project. A non-matched circuit will generate power losses as well as nasty reflection phenomena. (Refer to my article, “TDR Experiments,” Circuit Cellar 225, 2009.)

Impedance matching must be managed at the schematic stage, for example, by adding provisional matching pads for all integrated antennas, which will enable you to correct a slightly mis-adapted antenna (see Figure 1).

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Impedance matching is also a PCB design issue. As rule of thumb, you can’t avoid impedance-matched tracks when you are working with frequencies higher than the speed of light divided by 10 times the board size. A typical 10-cm board would translate to a cutoff frequency of 300 MHz. A digital designer would then say: “Cool, my clock is only 100 MHz. No problem!” But a 100-MHz square-ware clock or digital signal means harmonic frequencies in the gigahertz range, so it would be wise to show some concern.

The problem could also happen with very slow clocks when you’re using fast devices. Do you want an example? Last year, one of my colleagues developed a complex system with plenty of large and fast FPGAs. These chips were programmed through a common JTAG link and we ended up with nasty problems on the JTAG bus. We still had issues even when we slowed down the JTAG speed to 100 kHz. So, it couldn’t have been an impedance matching problem, right? Wrong. It was. Simply because the JTAG is managed by the FPGA with the same ultra-fast logic cells that manage your fast logic so with stratospheric skew rates which translated into very fast transitions on the JTAG lines. This generated ringing due to improper impedance matching, so there were false transitions on the bus. Such a problem was easy to solve once we pinpointed it, but we lost some days in between.—Robert Lacoste, CC25, 2013

 

SmartFusion2 Advanced Dev Kit

Microsemi Corp. has announced a new larges-density, low-power SmartFusion2 150K LE SoC FPGA Advanced Development Kit. It’s meant for board-level designers and system architects who need to rapidly create system-level designs.

Source: Microsemi Corp.

Source: Microsemi Corp.

The kit’s features include:

  • Largest 150K LE development device
  • 2x FMC connectors (HPC and LPC)
  • Purchase of kits comes with a free one-year Libero SoC design software platinum license (valued at $2,500)
  • DDR3, SPI flash
  • 2× Gigabit Ethernet connectors
  • SMA connectors
  • PCIe x4 edge connector
  • Power measurement test points

Source: Microsemi

 

Q&A: Electrical Engineer & FPGA Enthusiast

Chris Zeh is a San Jose, CA-based hardware design engineer who enjoys working with FPGA development boards, application-specific integrated circuits, and logic analyzers. He recently told us about the projects he is involved with at STMicroelectronics and explained what he’s working on in his free time.

CIRCUIT CELLAR: Tell us about Idle-Logic.com. Why and when did you decide to start a blog?

ZehCHRIS: I started blogging in the winter of 2009, a little more than a year after I graduated Colorado State University with a BSEE. I realized that after graduating it was important to continue working on various projects to keep my mind and skills sharp. I figured the best way to chronicle and show off my projects was to start a blog—my little corner of the Internet.

CIRCUIT CELLAR: What types of projects do you feature on your site?

CHRIS: I like working on a wide range of different types of projects, varying from software development to digital and analog design. I’ve found that most of my projects highlighted on Idle-Logic.com have been ones focusing on FPGAs. I find these little reprogrammable, multipurpose ICs both immensely powerful and fascinating to work with.

My initial plan for the blog was to start a development project to create an FPGA equivalent to the Arduino. I wanted to build a main board with all the basic hardware to run an Altera Cyclone II FPGA and then create add-on PCBs with various sensors and interfaces. My main FPGA board was to be named the Saturn board, and the subsequent add-on “wings” were to be named after the various moons of Saturn.

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

The project proceeded nicely. I spent some time brushing up on my Photoshop skills to put together a logo and came up with a minimized BOM solution to provide power to the nine different voltage supplies, both linear regulators and switched-mode supplies. One aspect of FPGAs that can make them costly for hobbyist is that the programming JTAG cable was on the order of $300. Fortunately, there are a few more affordable off-brand versions, which I used at first. After many weeks of work, I finally had the total solution for the main FPGA board. The total cost of the prototype system was about $150. Eventually I came up with a way to bit bang the FPGA’s programming bitstream using a simple $15 USB-to-UART IC breakout board driven by a tiny Python application, eliminating the need for the pricey cable. This Future Technology Devices International FT232RL USB-to-UART IC also provided a clock output enabling me to further reduce the component count.

The project was a success in that I was compelled to completely digest the FPGA’s 470-page handbook, giving me a solid grasp of how to work with FPGAs such as the Cyclone II. The project was a failure in that the FPGA breakout board I wanted to use for the project was discontinued by the manufacturer. Creating and fabricating my own four-layer board and hand soldering the 208-pin package was both prohibitively expensive and also a little daunting.

Fortunately, at that time Terasic Technologies introduced its DE0-Nano, a $79 commercial, $59 academic, feature-packed FPGA evaluation board. The board comes with two 40-pin general I/O plus power headers, which has become a perfect alternative base platform for FPGA development. I now intend to develop add-on “wings” to work with this evaluation board.

CIRCUIT CELLAR: Tell us more about how you’ve been using Terasic Technologies’s DE0-Nano development and education board.

CHRIS: The main project I’ve been working on lately with the DE0-Nano is creating and adding support for a full-color 4.3” (480 × 272 pixel) thin- film transistor (TFT) touchscreen LCD. Because of the large pin count available and reconfigurable logic, the DE0-Nano can easily support the display. I used a Waveshare Electronics $20 display, which includes a 40-pin header that is almost but not quite compatible with the DE0-Nano’s 40-pin header. Using a 40-pin IDC gray cable, I was able to do some creative rewiring (cutting and swapping eight or so pins) to enable the two to mate with minimal effort. Eventually, once all the features are tested, I’ll fabricate a PCB in place of the cable.

There are many libraries available to drive the display, but for this project I want to develop the hardware accelerators and video pipeline from the ground up, purely though digital logic in the FPGA. I recently picked up an SD card breakout board and a small camera breakout board. Using these I would like to start playing around with image processing and object recognition algorithms.

CIRCUIT CELLAR: What do you do at STMicroelectronics and what types of projects are you working on?

CHRIS: My official title is Senior Hardware Design Engineer. This title mainly comes thanks to the first project I worked on for the company, which is ongoing—an FPGA-based serial port capture and decoding tool named the HyperSniffer. However, my main role is that of an application engineer.

I spend most of my time testing and debugging our prototype mixed-signal ASICs prior to mass production. These ASICs are built for the hard disk drive industry. They provide several switch-mode power supplies, linear regulators, brushless DC motor controllers, voice coil motor actuation, and a shock sensor digital processing chain, along with the various DACs, ADCs, and monitoring circuits all integrated into a single IC.

Our ASIC’s huge feature set requires me to stay sharp on a wide variety of topics, both analog and digital. A typical day has me down in the lab writing scripts in Python or Visual Studio, creating stimuli, and taking measurements using my 1-GHz, 10-GSPS LeCroy WavePro 7100A oscilloscope, several 6.5-digit multimeters, dynamic signal analyzers, and noise injection power supplies among other instruments. I work closely with our international design team and our customers to help discover and document bugs and streamline the system integration.

A few years back I was able to join my colleagues in writing “Power Electronics Control to Reduce Hard Disk Drive Acoustics Pure Tones,” an Institute of Electrical and Electronics Engineers (IEEE) paper published for the Control and Modeling for Power Electronics (COMPEL) 2010 conference. I presented the paper, poster, and demonstration at the conference discussing a novel technique to reduce acoustic noise generated by a spindle motor.

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent Himpe and Albino Miglialo.)

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent
Himpe and Albino Miglialo.)

CIRCUIT CELLAR: Tell us more about the HyperSniffer project.

CHRIS: The HyperSniffer project is an FPGA- based digital design project I first created right out of college. (My colleagues Vincent Himpe and Albino Miglialo did the board design and layout.) The tool is basically an application-specific logic analyzer. It enables us to help our customers troubleshoot problems that arise from serial port transmissions between their system-on-a-chip (SoC) and our ASIC. Through various triggering options it can collect and decode the two or three wire data transmissions, store them on on- board memory, and wait for retrieval and further processing by the application running on the PC. One of this tool’s nice features is that it is capable of synchronizing and communicating with an oscilloscope, enabling us to track down problems that happen in the analog domain that arise due to commands sent digitally.

You can read the entire interview in Circuit Cellar 290 (September 2014).

DE0-Nano Cyclone FPGA Development Board

With a DE0-Nano Cyclone FPGA Development Board, you can create your own sophisticated hardware using programmable logic. The development board includes an Altera Cyclone IV and additional components to connect and test hardware designs. It comes a pre-wired Cyclone IV FPGA for programming and connection to internal or external devices and circuit.

Source: Parallax

Source: Parallax

With the board, you can create sophisticated logic hardware fairly quickly using a hardware description language. Possible applications include dedicated digital logic processors, robotics, and DIY autonomous systems.

Source: Parallax

Propeller Multicore MCU Released as Open-Source Design

Parallax released its source code design files for the Propeller 1 (P8X32A) multicore microcontroller at the DEFCON 22 Conference in Las Vegas, where the chip was also featured on the conference’s electronic badge. Parallax managers said they anticipate the release will inspire developers. Hobbyists, engineers, and students can now view and modify the Propeller Verilog design files by loading them into low-cost field programmable gate array (FPGA) development boards. The design was released under the GNU General Public License v3.0.

Source: Parallax

Source: Parallax

With the chip’s source code now available, any developer can discover what they need to know about the design. The open release provides a way for developers who have requested more pins, memory, or other architectural improvements to make their own version to run on an FPGA. Universities who have requested access to the design files for their engineering programs will now have them.

The Propeller multicore microcontroller is used in developing technologies where multiple sensors, user interface systems, and output devices such as motors must be managed simultaneously. Some primary applications for Parallax’s chip include flight controllers in UAVs, 3-D printing, solar monitoring systems, environmental data collection, theatrical lighting and sound control, and medical devices.

For more information on Parallax’s open source release of the Propeller P8X32A, visit www.parallax.com.

 

Embedded SOM with Linux-Based RTOS

National Instruments has introduced an embedded system-on-module (SOM) development board with integrated Linux-based real-time operating system (RTOS).NIsom

Processing power in the 2” x 3” SOM comes from a Xilinx Zync-7020 all programmable SOC running a dual core ARM Cortex-A9 at 667 MHz. A built-in, low-power Artix-7 FPGA offers 160 single-ended I/Os and Its dedicated processor I/O include Gigabit Ethernet USB 2.0 host, USB 2.0 host/device, SDHC, RS-232, and Tx/Rx. The SOM’s power requirements are typically 3 to 5 W.

The SOM integrates a validated board support package (BSP) and device drivers together with the National Instruments Linux real-time OS. The SOM board is supplied with a full suite of middleware for developing an embedded OS, custom software drivers, and other common software components.

The LabVIEW FPGA graphical development platform eliminates the need for expertise in the design approach using a hardware description language.

[Via Elektor]

 

SDK for OpenCL Dev Flow

Altera Corp. has simplified a programmer’s ability to accelerate algorithms in FPGAs. The Altera SDK for OpenCL version 14.0 includes a programmer-familiar rapid prototyping design flow that enables users to prototype designs in minutes on an FPGA accelerator board. Altera, along with its board partners, further accelerate the development of FPGA-based applications by offering reference designs, reference platforms and FPGA development boards that are supported by Altera’s OpenCL solution. These reference platforms also streamline the development of custom FPGA accelerators to meet specific application requirements.

Altera is the only company to offer a publicly available, OpenCL conformant software development kit (SDK). The solution allows programmers to develop algorithms with the C-based OpenCL language and harness the performance and power efficiencies of FPGAs. A rapid prototyping design flow included in the Altera SDK for OpenCL version 14.0 allows OpenCL kernel code to be emulated, debugged, optimized, profiled and re-compiled to a hardware implementation in minutes. The re-compiled kernels can be tested and run on an FPGA immediately, saving programmers weeks of development time.

Altera and its board partners further simplify the experience of getting applications up and running using FPGA accelerators by offering a broad selection of Altera-developed reference platforms, reference designs and FPGA accelerator boards. Altera provides a variety of design examples that demonstrate how to describe applications in OpenCL, including OPRA FAST Parser for finance applications, JPEG decoder for big data applications and video downscaling for video applications.

Design teams that want to create custom solutions that feature a unique set of peripherals can create their own custom FPGA accelerators and save significant development time by using Altera-developed reference platforms. The reference platforms include an SoC platform for embedded applications, a high-performance computing (HPC) platform and a low-latency network enabled platform which utilizes IO Channels.

One notable enhancement is production support for I/O Channels that allow streaming data into and out of the FPGA as well as kernel channels allowing the result reuse from one kernel to another in a hardware pipeline for significantly higher performance and throughput with little to no host and memory interaction. Another enhancement is production support for single-chip SoC solutions (Cyclone V SoC and Arria V SoC), where the host is an embedded ARM core processor integrated in the FPGA accelerator.

Altera’s SDK for OpenCL allows programmers to take OpenCL code and rapidly exploit the massively parallel architecture of an FPGA. Programmers targeting FPGAs achieve higher performance at significantly lower power compared to alternative hardware architectures, such as GPUs and CPUs. On average, FPGAs deliver higher performance at one-fifth the power of a GPU. Altera’s OpenCL solutions are supported by third-party boards through the Altera Preferred Board Partner Program for OpenCL. Visit www.altera.com/opencl.

The Altera SDK for OpenCL is currently available for download on Altera’s website (www.altera.com/products/software/opencl/opencl-index.html). The annual software subscription for the SDK for OpenCL is $995 for a node-locked PC license. For additional information about the Altera Preferred Board Partner Program for OpenCL and its partner members, or to see a list of all supported boards and links to purchase, visit the OpenCL section on Altera’s website.

[Source: Altera Corp.]

Robotics, Hardware Interfacing, and Vintage Electronics

Gerry O’Brien, a Toronto-based robotics and electronics technician at R.O.V. Robotics, enjoys working on a variety of projects in his home lab. His projects are largely driven by his passion for electronics hardware interfacing.

Gerry’s background includes working at companies such as Allen-Vanguard Corp., which builds remotely operated vehicle (ROV) robots and unmanned ground vehicles (UGVs) for military and police bomb disposal units worldwide. “I was responsible for the production, repair, programming and calibration of the robot control consoles, VCU (vehicle control unit) and the wireless communication systems,” he says.

Gerry recently sent Circuit Cellar photos of his home-based electronics and robotics lab. (More images are available on his website.) This is how he describes the lab’s layout and equipment:

In my lab I have various designated areas with lab benches that I acquired from the closing of a local Nortel  R&D office over 10 years ago.

All of my electronics benches have ESD mats and ground wrist straps.  All of my testing gear, I have purchased on eBay over the years….

PCB flip rack

PCB flip-rack

To start, I have my “Electronics Interfacing Bench” with a PCB flip-rack , which allows me to Interface PCBs while they are powered (in-system testing). I am able to interface my Tektronix TLA715 logic analyzer and other various testing equipment to the boards under test. My logic analyzer currently has two  logic I/O modules that have 136 channels each. So combined, I have 272 channels for logic analysis. I also have a four-channel digital oscilloscope module to use with this machine. I can now expand this even further by interfacing my newly acquired expansion box, which allows me to interface many more modules to the logic analyzer mainframe.

Gerry's lab bench

Gerry’s lab bench

Gerry recently upgraded his  Tektronix logic analyzer with an expansion box.

Gerry recently upgraded his Tektronix logic analyzer with an expansion box.

Interface probes

Logic analyzer interface probes

I also have a soldering bench where I have all of my soldering gear, including a hot-air rework station and 90x dissecting microscope with a video interface.

Dissecting microscope with video interface

Dissecting microscope with video interface

My devoted robotics bench has several robotic arm units, Scorbot and CRS robots with their devoted controllers and pneumatic Interface control boards.

Robotics bench

Robotics bench and CRS robot

On my testing bench, I currently have an Agilent/HP 54610B 500-MHz oscilloscope with the GPIB to RS-232 adapter for image capturing. I also have an Advantest model R3131A 9 kHz to 3-GHz bandwidth spectrum analyzer, a Tektronix model AFG3021 function generator, HP/Agilent 34401A multimeter and an HP 4CH programmable power supply. For the HP power supply, I built a display panel with four separate voltage output LCD displays, so that I can monitor the voltages of all four outputs simultaneously. The stock monochrome LCD display on the HP unit itself is very small and dim and only shows one output at a time.

Anyhow, my current testing bench setup will allow me to perform various signal mapping and testing on chips with a large pin count, such as the older Altera MAX9000 208-pin CPLDs and many others that I enjoy working with.

The testing bench

The testing bench

And last but not least… I have my programming and interfacing bench devoted to VHDL programming, PCB Design, FPGA hardware programming (JTAG), memory programming (EEPROM  and flash memory), web design, and video editing.

Interfacing bench and "octo-display"

Interfacing bench and “octo-display”

I built a PC computer and by using  a separate graphics display cards, one being an older Matrols four-port SVGA display card; I was able to build a “octo-display” setup. It seamlessly shares eight monitors providing a total screen resolution size of 6,545 x 1,980 pixels.

If you care to see how my monitor mounting assembly was built, I have posted pictures of its construction here.

A passion for electronics interfacing drives Gerry’s work:

I love projects that involve hardware Interfacing.  My area of focus is on electronics hardware compared to software programming. Which is one of the reasons I have focused on VHDL programming (hardware description language) for FPGAs and CPLDs.

I leave the computer software programming of GUIs to others. I will usually team up with other hobbyists that have more of a Knack for the Software programming side of things.  They usually prefer to leave the electronics design and hardware production to someone else anyhow, so it is a mutual arrangement.

I love to design and build projects involving vintage Altera CPLDs and FPGAs such as the Altera MAX7000 and MAX9000 series of Altera components. Over the years, I have a managed to collect a large arsenal of vintage Altera programming hardware from the late ’80s and early ’90s.  Mainly for the Altera master programming unit (MPU) released by Altera in the early ’90s. I have been building up an arsenal of the programming adapters for this system. Certain models are very hard to find. Due to the rarity of this Altera programming system, I am currently working on designing my own custom adapter interface that will essentially allow me to connect any compatible Altera component to the system… without the need of the unique adapter. A custom made adapter essentially.  Not too complicated at all really, it’s just a lot of fun to build and then have the glory of trying out other components.

I love to design, build, and program FPGA projects using the VHDL hardware description language and also interface to external memory and sensors. I have a devoted website and YouTube channel where I post various hardware repair videos or instructional videos for many of my electronics projects. Each project has a devoted webpage where I post the instructional videos along with written procedures and other information relating to the project. Videos from “Robotic Arm Repair” to a “DIY SEGA Game Gear Flash Cartridge” project. I even have VHDL software tutorials.

The last project I shared on my website was a project to help students dive into a VHDL based VGA Pong game using the Altera DE1 development board.

 

FPGA Partial Reconfiguration

Many field-programmable gate array (FPGA) design modules have parameters, such as particular clock and I/O drive settings, that can only be adjusted during implementation, not at runtime. However, being able to make such adjustments in an FPGA design during operation is convenient.

In Circuit Cellar’s June issue, columnist Colin O’Flynn addresses how to use partial reconfiguration (PR) to sidestep such restrictions. Using difference-based PR, you can adjust digital clock module (DCM) attributes, I/O drive strength, and even look-up-table (LUT) equations, he says. O’Flynn’s article describes how he used PR on a Xilinx Spartan-6 FPGA to solve a specific problem. The article excerpt below elaborates:

Perfect Timing
The digital clock module (DCM) in a Xilinx Spartan-6 FPGA has a variety of features, including the ability to add an adjustable phase shift onto an input clock.

There are two types of phase shifts: fixed and variable. A fixed shift can vary from approximately –360° to 360° in 1.4° steps. A variable shift enables shifting over a smaller range, which is approximately ±5 nS in 30-ps steps.

Note the actual range and step size varies considerably for different operating conditions. Hence the problem: the provided variable phase shift interface is only useful for small phase shifts; any major phase shift must be fixed at design time.

To demonstrate how PR can be used to fix the problem, I’ll generate a design that implements a DCM block and use PR to dynamically reconfigure the DCM.

Figure 1—The system’s general block diagram is shown. A digital clock module (DCM) block synthesizes a new clock from the system oscillator and then outputs the clock to an I/O pin. The internal configuration access port (ICAP) interface is used to load configuration data. The serial interface connects the ICAP interface to a computer via a first in, first out (FIFO) buffer.

Figure 1—The system’s general block diagram is shown. A digital clock module (DCM) block synthesizes a new clock from the system oscillator and then outputs the clock to an I/O pin. The internal configuration access port (ICAP) interface is used to load configuration data. The serial interface connects the ICAP interface to a computer via a first in, first out (FIFO) buffer.

Streaming Bits
I used Xilinx’s ISE design suite to generate a design (see Figure 1). I did the usual step of creating the entire FPGA bitstream, which could then be programmed into the FPGA. The FPGA bitstream is essentially a completely binary blob tells you nothing about your design. The “FPGA native circuit description (NCD)” file is one step above the FPGA bitstream. The NCD file contains a complete description of the design mapped to the blocks available in your specific chip with all the routing of signals between those blocks and useful net names.

The NCD file contains enough information for you to do some edits to the FPGA design. Then you can use the NCD file to generate a new binary blob (bitstream) for programming. A critical part of PR is understanding that when you download this new blob, you can only download the difference between the original file and the new file. This is known as “difference-based PR,” and it is the only type of PR I’ll be discussing.

So what’s in the bitstream? The bitstream actually contains several different commands sent to the FPGA device, which instructs the FPGA to load configuration information, tells it the address information where the data is going to be loaded, and finally sends the actual data to load. Given a bitstream file, you can actually parse this information out. I’ve posted a Python script on ProgrammableLogicInPractice.com that does this for the Spartan-6 device.

A frame is the smallest portion of an FPGA that can be configured. The frame’s size varies per device. (For the Spartan-6 I used in this article, it is 65 × 16-bit words, or 1,040 bits per frame.) You must reload the entire frame if anything inside it changes, which brings me to the first “gotcha.” When using PR, everything inside that “frame” will be reloaded (i.e., parts of your design that haven’t changed may become temporarily invalid because they share a configuration frame with the part of your design that has changed).

O’Flynn’s full article goes on to explain more about framing, troubleshooting challenges along the way, and completing the reconfiguration. The article is available in the June issue, now available for membership download or single-issue purchase.

To further assist readers, O’Flynn has posted more information on the website that complements his monthly Circuit Cellar column, including a video of his project running.

“You can also see an example of how I integrated PR into my open-source ChipWhisperer project, which uses PR to dynamically program a phase shift into the DCMs inside the FPGA,” he says.