Impedance Matching Matters (EE Tip #145)

RF designers, as well as more and more digital-oriented designers, are used to thinking about impedance matching. But it is very easy to forget it when you are designing a non-RF project. A non-matched circuit will generate power losses as well as nasty reflection phenomena. (Refer to my article, “TDR Experiments,” Circuit Cellar 225, 2009.)

Impedance matching must be managed at the schematic stage, for example, by adding provisional matching pads for all integrated antennas, which will enable you to correct a slightly mis-adapted antenna (see Figure 1).

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Impedance matching is also a PCB design issue. As rule of thumb, you can’t avoid impedance-matched tracks when you are working with frequencies higher than the speed of light divided by 10 times the board size. A typical 10-cm board would translate to a cutoff frequency of 300 MHz. A digital designer would then say: “Cool, my clock is only 100 MHz. No problem!” But a 100-MHz square-ware clock or digital signal means harmonic frequencies in the gigahertz range, so it would be wise to show some concern.

The problem could also happen with very slow clocks when you’re using fast devices. Do you want an example? Last year, one of my colleagues developed a complex system with plenty of large and fast FPGAs. These chips were programmed through a common JTAG link and we ended up with nasty problems on the JTAG bus. We still had issues even when we slowed down the JTAG speed to 100 kHz. So, it couldn’t have been an impedance matching problem, right? Wrong. It was. Simply because the JTAG is managed by the FPGA with the same ultra-fast logic cells that manage your fast logic so with stratospheric skew rates which translated into very fast transitions on the JTAG lines. This generated ringing due to improper impedance matching, so there were false transitions on the bus. Such a problem was easy to solve once we pinpointed it, but we lost some days in between.—Robert Lacoste, CC25, 2013

 

SmartFusion2 Advanced Dev Kit

Microsemi Corp. has announced a new larges-density, low-power SmartFusion2 150K LE SoC FPGA Advanced Development Kit. It’s meant for board-level designers and system architects who need to rapidly create system-level designs.

Source: Microsemi Corp.

Source: Microsemi Corp.

The kit’s features include:

  • Largest 150K LE development device
  • 2x FMC connectors (HPC and LPC)
  • Purchase of kits comes with a free one-year Libero SoC design software platinum license (valued at $2,500)
  • DDR3, SPI flash
  • 2× Gigabit Ethernet connectors
  • SMA connectors
  • PCIe x4 edge connector
  • Power measurement test points

Source: Microsemi

 

Q&A: Electrical Engineer & FPGA Enthusiast

Chris Zeh is a San Jose, CA-based hardware design engineer who enjoys working with FPGA development boards, application-specific integrated circuits, and logic analyzers. He recently told us about the projects he is involved with at STMicroelectronics and explained what he’s working on in his free time.

CIRCUIT CELLAR: Tell us about Idle-Logic.com. Why and when did you decide to start a blog?

ZehCHRIS: I started blogging in the winter of 2009, a little more than a year after I graduated Colorado State University with a BSEE. I realized that after graduating it was important to continue working on various projects to keep my mind and skills sharp. I figured the best way to chronicle and show off my projects was to start a blog—my little corner of the Internet.

CIRCUIT CELLAR: What types of projects do you feature on your site?

CHRIS: I like working on a wide range of different types of projects, varying from software development to digital and analog design. I’ve found that most of my projects highlighted on Idle-Logic.com have been ones focusing on FPGAs. I find these little reprogrammable, multipurpose ICs both immensely powerful and fascinating to work with.

My initial plan for the blog was to start a development project to create an FPGA equivalent to the Arduino. I wanted to build a main board with all the basic hardware to run an Altera Cyclone II FPGA and then create add-on PCBs with various sensors and interfaces. My main FPGA board was to be named the Saturn board, and the subsequent add-on “wings” were to be named after the various moons of Saturn.

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

The project proceeded nicely. I spent some time brushing up on my Photoshop skills to put together a logo and came up with a minimized BOM solution to provide power to the nine different voltage supplies, both linear regulators and switched-mode supplies. One aspect of FPGAs that can make them costly for hobbyist is that the programming JTAG cable was on the order of $300. Fortunately, there are a few more affordable off-brand versions, which I used at first. After many weeks of work, I finally had the total solution for the main FPGA board. The total cost of the prototype system was about $150. Eventually I came up with a way to bit bang the FPGA’s programming bitstream using a simple $15 USB-to-UART IC breakout board driven by a tiny Python application, eliminating the need for the pricey cable. This Future Technology Devices International FT232RL USB-to-UART IC also provided a clock output enabling me to further reduce the component count.

The project was a success in that I was compelled to completely digest the FPGA’s 470-page handbook, giving me a solid grasp of how to work with FPGAs such as the Cyclone II. The project was a failure in that the FPGA breakout board I wanted to use for the project was discontinued by the manufacturer. Creating and fabricating my own four-layer board and hand soldering the 208-pin package was both prohibitively expensive and also a little daunting.

Fortunately, at that time Terasic Technologies introduced its DE0-Nano, a $79 commercial, $59 academic, feature-packed FPGA evaluation board. The board comes with two 40-pin general I/O plus power headers, which has become a perfect alternative base platform for FPGA development. I now intend to develop add-on “wings” to work with this evaluation board.

CIRCUIT CELLAR: Tell us more about how you’ve been using Terasic Technologies’s DE0-Nano development and education board.

CHRIS: The main project I’ve been working on lately with the DE0-Nano is creating and adding support for a full-color 4.3” (480 × 272 pixel) thin- film transistor (TFT) touchscreen LCD. Because of the large pin count available and reconfigurable logic, the DE0-Nano can easily support the display. I used a Waveshare Electronics $20 display, which includes a 40-pin header that is almost but not quite compatible with the DE0-Nano’s 40-pin header. Using a 40-pin IDC gray cable, I was able to do some creative rewiring (cutting and swapping eight or so pins) to enable the two to mate with minimal effort. Eventually, once all the features are tested, I’ll fabricate a PCB in place of the cable.

There are many libraries available to drive the display, but for this project I want to develop the hardware accelerators and video pipeline from the ground up, purely though digital logic in the FPGA. I recently picked up an SD card breakout board and a small camera breakout board. Using these I would like to start playing around with image processing and object recognition algorithms.

CIRCUIT CELLAR: What do you do at STMicroelectronics and what types of projects are you working on?

CHRIS: My official title is Senior Hardware Design Engineer. This title mainly comes thanks to the first project I worked on for the company, which is ongoing—an FPGA-based serial port capture and decoding tool named the HyperSniffer. However, my main role is that of an application engineer.

I spend most of my time testing and debugging our prototype mixed-signal ASICs prior to mass production. These ASICs are built for the hard disk drive industry. They provide several switch-mode power supplies, linear regulators, brushless DC motor controllers, voice coil motor actuation, and a shock sensor digital processing chain, along with the various DACs, ADCs, and monitoring circuits all integrated into a single IC.

Our ASIC’s huge feature set requires me to stay sharp on a wide variety of topics, both analog and digital. A typical day has me down in the lab writing scripts in Python or Visual Studio, creating stimuli, and taking measurements using my 1-GHz, 10-GSPS LeCroy WavePro 7100A oscilloscope, several 6.5-digit multimeters, dynamic signal analyzers, and noise injection power supplies among other instruments. I work closely with our international design team and our customers to help discover and document bugs and streamline the system integration.

A few years back I was able to join my colleagues in writing “Power Electronics Control to Reduce Hard Disk Drive Acoustics Pure Tones,” an Institute of Electrical and Electronics Engineers (IEEE) paper published for the Control and Modeling for Power Electronics (COMPEL) 2010 conference. I presented the paper, poster, and demonstration at the conference discussing a novel technique to reduce acoustic noise generated by a spindle motor.

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent Himpe and Albino Miglialo.)

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent
Himpe and Albino Miglialo.)

CIRCUIT CELLAR: Tell us more about the HyperSniffer project.

CHRIS: The HyperSniffer project is an FPGA- based digital design project I first created right out of college. (My colleagues Vincent Himpe and Albino Miglialo did the board design and layout.) The tool is basically an application-specific logic analyzer. It enables us to help our customers troubleshoot problems that arise from serial port transmissions between their system-on-a-chip (SoC) and our ASIC. Through various triggering options it can collect and decode the two or three wire data transmissions, store them on on- board memory, and wait for retrieval and further processing by the application running on the PC. One of this tool’s nice features is that it is capable of synchronizing and communicating with an oscilloscope, enabling us to track down problems that happen in the analog domain that arise due to commands sent digitally.

You can read the entire interview in Circuit Cellar 290 (September 2014).

DE0-Nano Cyclone FPGA Development Board

With a DE0-Nano Cyclone FPGA Development Board, you can create your own sophisticated hardware using programmable logic. The development board includes an Altera Cyclone IV and additional components to connect and test hardware designs. It comes a pre-wired Cyclone IV FPGA for programming and connection to internal or external devices and circuit.

Source: Parallax

Source: Parallax

With the board, you can create sophisticated logic hardware fairly quickly using a hardware description language. Possible applications include dedicated digital logic processors, robotics, and DIY autonomous systems.

Source: Parallax

Propeller Multicore MCU Released as Open-Source Design

Parallax released its source code design files for the Propeller 1 (P8X32A) multicore microcontroller at the DEFCON 22 Conference in Las Vegas, where the chip was also featured on the conference’s electronic badge. Parallax managers said they anticipate the release will inspire developers. Hobbyists, engineers, and students can now view and modify the Propeller Verilog design files by loading them into low-cost field programmable gate array (FPGA) development boards. The design was released under the GNU General Public License v3.0.

Source: Parallax

Source: Parallax

With the chip’s source code now available, any developer can discover what they need to know about the design. The open release provides a way for developers who have requested more pins, memory, or other architectural improvements to make their own version to run on an FPGA. Universities who have requested access to the design files for their engineering programs will now have them.

The Propeller multicore microcontroller is used in developing technologies where multiple sensors, user interface systems, and output devices such as motors must be managed simultaneously. Some primary applications for Parallax’s chip include flight controllers in UAVs, 3-D printing, solar monitoring systems, environmental data collection, theatrical lighting and sound control, and medical devices.

For more information on Parallax’s open source release of the Propeller P8X32A, visit www.parallax.com.