FPGA-Based Storage Reference Design Doubles NAND Flash Life

Altera Corp. recently developed a storage reference design  based on its Arria 10 SoCs that doubles the life of NAND flash. In addition, can increase the number of program-erase cycles by up to 7×. The design features an Arria 10 SoC with an integrated dual-core ARM Cortex A9 processor in an optimized, single-chip solution. It uses a Mobiveil SSD controller and NVMdurance NAND optimization software. This reference design provides improved performance and flexibility in NAND utilization while reducing the cost of the NAND array by increasing the lifetime of data center equipment.NAND_AlteraMobiveil’s controller supports multi-core architectures, enabling threads to run on each core with their own queue and interrupt without any locks required. NVMdurance’s NAND flash optimization software monitors the NAND Flash’s condition and automatically adjusts the control parameters in real time. The reference design also features end-to-end data protection, encryption and compression, and optimizes throughput and power consumption, all in a small silicon footprint.

Altera’s NAND storage reference design is available today.

Source: Altera Corp.

ZestET2-NJ Gigabit Ethernet FPGA Module

Orange Tree Technologies recently launched the ZestET2-NJ high-performance Gigabit Ethernet FPGA module, which comprises a Gigabit Ethernet processing engine, Xilinx Artix-7 FPGA, DDR3 memory, and general-purpose I/O. Delivering the maximum sustained Ethernet bandwidth of over 100 MBps in both directions simultaneously, it is aimed at data acquisition and control applications in markets such as industrial vision, radar, sonar and medical imaging.OrangeTree-zestet2-nj

The Xilinx Artix-7 XC7A35T FPGA, which has more than 33,000 logic cells, 1.8 Mb of Block RAM and 90 DSP slices, is tightly coupled with 512 MB of 400-MHz DDR3 SDRAM, giving it an ample memory bandwidth of 1.6 GBps for high-speed processing and formatting of streaming data.  With ease of integration in mind, there are 105 FPGA I/O pins available for connection to the user’s equipment.

Orange Tree’s proprietary GigEx chip handles the entire TCP/IP stack at over 100 MBps in each direction simultaneously. It enables the User FPGA to be dedicated entirely to the application for maximum efficiency.  The module measures just 40 × 50 mm, making it ideal for integration into your products.

Source: Orange Tree Technologies

USB-to-FPGA Communications: A Case Study of the ChipWhisperer-Lite

Sending data from a computer to an FPGA is often required. This might be FPGA configuration data, register settings, or streaming data. An easy solution is to use a USB-connected microcontroller instead of a dedicated interface chip, which allows you to offload certain tasks into the microcontroller.

In Circuit Cellar 299 (June 2015), Colin O’Flynn writes:

Often your FPGA-based project will require computer communication and some housekeeping tasks. A popular solution is the use of a dedicated USB interface chip, and a soft-core processor in the FPGA for housekeeping tasks.

For an open-source hardware project I recently launched, I decided to use an external USB microcontroller instead of a dedicated interface chip. I suspect you’ll find a lot of useful design tidbits you can use for yourself—and, because it’s open source, getting details of my designs doesn’t involve industrial espionage!

The design is called the ChipWhisperer-Lite (see Photo 1). This device is a training aid for learning about side-channel power analysis of cryptographic implementations. Side-channel power analysis uses measurements of small power variations during execution of the cryptographic algorithms to break the implementation of the algorithm.

Photo 1: This shows the ChipWhisperer-Lite, which contains a Xilinx Spartan 6 LX9 FPGA and Atmel SAM3U2C microcontroller. The remaining circuitry involves the power supplies, ADC, analog processing, and a development device which the user programs with some cryptographic algorithm they are analyzing.

Photo 1: This shows the ChipWhisperer-Lite, which contains a Xilinx Spartan 6 LX9 FPGA and Atmel SAM3U2C microcontroller. The remaining circuitry involves the power supplies, ADC, analog processing, and a development device which the user programs with some cryptographic algorithm they are analyzing.

In a previous article, “Build a SoC Over Lunch” (Circuit Cellar 289, 2014), I made the case for using a soft-core processing in an FPGA. In this article I’ll play the devil’s advocate by arguing that using an external microcontroller is a better choice. Of course the truth lies somewhere in between: in this example, the requirement of having a high-speed USB interface makes an external microcontroller more cost-effective, but this won’t always be the case.

This article assumes you require computer communication as part of your design. There are many options for this. The easiest from a hardware perspective is to use a USB-Serial converter, and many projects use such a system. The downside is a fairly slow interface, and the requirement of designing a serial protocol.

A more advanced option is to use a USB adapter with a parallel interface, such as the FTDI FT2232H. These can achieve very high-speed data rates—basically up to the limit of the USB 2.0 interface. The downside of these options is that it still requires some protocol implemented on your FPGA for many applications, and it has limited extra features (such as if you need housekeeping tasks).

The solution I came to is the use of a USB microcontroller. They are widely available from most vendors with USB 2.0 high-speed (full 480 Mbps data rate) interfaces, and allow you to perform not only the USB interface, but the various housekeeping tasks that your system will require. The USB microcontroller will also likely be around the same price (or possibly cheaper) than the equivalent specialized interface chip.

When selecting a microcontroller, I recommend finding one with an external memory bus interface. This external memory bus is normally designed to allow you to map devices such as SRAM or DRAM into the memory space of the microcontroller. In our case we’ll actually be mapping FPGA registers into the microcontroller memory space, which means we don’t need any protocol for communication with the FPGA.


Figure 1: This figure shows the basic connections used for memory-mapping the FPGA into the microcontroller memory space. Depending on your requirements, you can add some additional custom lines, such as a flag to indicate different FPGA register banks to use, as only a 9-bit address bus is used in this example.

I selected an Atmel SAM3U2C microcontroller, which has a USB 2.0 high-speed interface. This microcontroller is low-cost and available in TQFP package, which is convenient if you plan on hand assembling prototype boards. The connections between the FPGA and microcontroller are shown in Figure 1.

On the FPGA, it is easy to map this data bus into registers. This means that to configure some feature in the FPGA, you can just directly write into a register. Or if you are transferring data, you can read from or write to a block-RAM (BRAM) implemented in the FPGA.

Check out Colin’s ChipWhisperer-Lite KickStarter Video:

New High-Performance VC Z Series Cameras

Vision Components recently announced the availability of its new intelligent camera series VC Z. The embedded systems offer real-time image processing suitable for demanding high-speed and line scan applications. All models are equipped with Xilinx’s Zynq module, an ARM dual-core Cortex-A9 with 866 MHz and an integrated FPGA.Vision Components - VC_Z_series_stapel_pingu

The new camera is based on the board camera series VCSBC nano Z. With a footprint of 40 × 65 mm, these compact systems are especially easy to integrate into machines and plants. They are optionally available with one or two remote sensor heads and thus suitable for stereo applications.You can choose between two enclosed camera types: the VC nano Z, which has housing dimensions of 80 × 45 × 20 mm, and the VC pro Z, which measures 90 × 58 × 36 mm and can be fitted with a lens and an integrated LED illumination. The new operating system VC Linux ensures optimal interaction between hardware and software.

Source: Vision Components

Engineering “Moonshot” Projects

In 2009, Andrew Meyer, an MIT-trained engineer and entrepreneur, co-founded LeafLabs, a Cambridge, MA-based R&D firm that designs “powerful physical computing devices for control and communication among smart machines (including humans).” We recently asked Andrew to tell us about his background, detail some of his most intriguing projects, tell us about his contributions to Project Ara, and share his thoughts on the future of electrical engineering.AndrewMeyerLeaflabs

CIRCUIT CELLAR: How did you become interested in electronics? Did you start at a young age?

ANDREW: Yes, actually, but I am not sure I really got anywhere fooling around as a kid. I had a deep love of remote control cars and airplanes in middle school. I was totally obsessed with figuring out how to build my own control radio. This was right before the rise of Google, and I scoured the net for info on circuits. In the end, I achieved a reasonable grasp on really simple RC type circuits but completely failed in figuring out the radio. Later in high school I took some courses at the local community college and built an AM radio and got into the math for the first time – j and omega and all that.

CIRCUIT CELLAR: What is Leaflabs? How did it start? Who comprises your team today?

ANDREW: LeafLabs is an R&D firm specializing in embedded and distributed systems. Projects start as solving specific problems for a client, but the idea is to turn those relationships into product opportunities. To me, that’s what separates R&D from consulting.


The LeafLabs Office (Source: LeafLabs)

I started LeafLabs with a handful of friends in 2009. It was an all MIT cast of engineers, and it took four or five years before I understood how much we were holding ourselves back by not embracing some marketing and sales talent. The original concept was to try and design ICs that were optimized for running certain machine learning algorithms at low power. The idea was that smartphones might want to do speech to text some day without sending the audio off to the cloud. This was way too ambitious for a group of 22 year olds with no money.

Our second overly ambitious idea was to try and solve the “FPGA problem.” I’m still really passionate about this, but it too was too much for four kids in a basement to take a big bite off. The problem is that FPGAs vendors like Xilinx and Altera have loads of expertise in silicon, but great software is just not in their DNA. Imagine if x86 never published their instruction set. What if Intel insisted on owning not just the processors, but the languages, compilers, libraries, IDEs, debuggers, operating systems, and the rest of it? Would we ever have gotten to Linux? What about Python? FPGAs have enormous potential to surpass even the GPU as a completely standard technology in computer systems. There should some gate fabric in my phone. The development tools just suck, suck, suck. If any FPGA executives are reading this: Please open up your bitstream formats, the FSF and the rest of the community will get the ball rolling on an open toolchain that will far exceed what you guys are doing internally. You will change the world.

CIRCUIT CELLAR: How did the Maple microcontroller board come about?

ANDREW: Arduino was really starting to come up at the time. I had just left Analog, where we had been using the 32-bit Cortex M3. We started asking “Chips like the STM32 are clearly the way of the future, why on earth is Arduino using a chip from the ‘90s?” Perry, another LeafLabs founder, was really passionate about this. ARM is taking over the world, the community deserves a product that is as easy to use as Arduino, but built on top of modern technology.

CIRCUIT CELLAR: Can you give a general overview of your involvement with Project Ara?

ANDREW: We got into Ara at the beginning as subcontractors to the company that was leading a lot of the engineering, NK Labs. Since then our role has expanded quite a bit, but we are still focused on software and firmware development. Everyone understood that Ara was going to require a lot of firmware and FPGA work, and so we were a natural choice to get involved. One of the first Ara prototypes actually used the Maple software library, libmaple, and had eight FPGAs in it! For your readers that are interested in Ara, please to check out projectara.com and https://github.com/projectara/greybus/.

LeafLabs is focused on firmware development. What’s really exciting to me about the project is the technology under the hood. Basically, what we have done is built a network on a PCB. The first big problem with embedded linux devices is that they are completely centered around the SoC. Change the SoC and you are in for ton of software development, for instance, to bring your display driver back to life. Similarly, changes to the design, such as incorporating a faster Wi-Fi chip, might force you to change the SoC. This severe coupling between everything keeps designers from iterating. You have this attitude of “OK, no one touch this design for the next 5 years, we finally got it working.” If we have learned anything from SaaS and App companies it’s that quickly iterating and continuous deployment are key to great products. If your platform inhibits iteration, you have a big problem.

The other problem with embedded systems is that there are so many protocols! SDIO, USB, DSI, I2C, SPI, CSI, blah blah blah. Do we really need so many!? Think how much mileage we get out of TCP/IP. The protocol explosion just adds impedance to the entire design process, and forces engineers to be worrying about bits toggling on traces rather than customer facing features.

The technology being developed for Ara, called Greybus, solves both these problems. The centerpiece of our phone is a switch, and the display, Wi-Fi, audio, baseband, etc all hang off the switch as network devices. Even the processor is just another module hanging off this network. All modules speak the same “good enough” protocol called UniPro (Unified Protocol). The possibilities here are absolutely tantalizing. To learn more about Greybus, see here: https://github.com/projectara/greybus/.

CIRCUIT CELLAR: Can you define “minimalist data acquisition” for our readers? What is it and why does it interest you?

ANDREW: More and more fields, but particularly in neuroscience, are having to deal with outrageously huge real-time data sets. There are 100 billion neurons in the human brain. If we want to listen to just 1,000 of them, we are already talking about ~1 Gbps. Ed Boyden, a professor at MIT, asked us if we could build some hardware to help handle the torrent. Could we scale to 1 Tbps? Could we build something that researchers on a budget could actually afford and that mere mortals could use?

The Willow (Source: LeafLabs)

The Willow (Source: LeafLabs)

Willow is a hardware platform for capturing, storing, and processing neuroscience data at this scale. We had to be “minimalist” to keep costs down, and ensure our system is easy to use. Since we need to use an FPGA anyway to interface with a data source (like a bank of ADCs, or an array of image sensors), we thought, “Why not use the same chip for interfacing to storage?” With a single $150 FPGA and a couple of $200 SSD drives, we can record at 12 Gbps, put guarantees on throughput, and record for a couple of hours!

CIRCUIT CELLAR: What are you goals for LeafLabs for the next 6 to 12 months?

ANDREW: Including our superb remote contractors, our team is pushing 20. A year from now, it could be double that. This is a really tricky transition—where company culture really starts to solidify, where project management becomes a first-order problem, and where people’s careers are on the line. My first goal for LeafLabs is make sure we nail this transition and build off of a really solid foundation. Besides that, we are always looking for compelling new problems to work on and new markets to play in. Getting into neuroscience has been an absolute blast.

The complete interview appears in Circuit Cellar 298 (May 2015).

Low-Profile PCIe Board Platform

BittWare recently announced today its second low-profile PCIe board—the A5-PCIe-S (A5PS). The new board is based on Altera’s Arria V GZ FPGA, which provides a high level of system integration and flexibility for I/O, routing, and processing. Thus, the A5PS is a reliable platform for a variety of applications (e.g., network processing, security, broadcast, and signals intelligence).BittWare A5PS

Featuring dual SFP+ cages that run up to 12.5 Gbps, the A5PS provides dual 10GigE ports using optical transceivers as well as passive copper cabling up to 7 m. These ports are serviced by the advanced 28-nm Arria V GZ FPGA, which also supports a Gen3 x8 PCIe interface and either 8-GB DDR3 or 36-MB QDRII+. Sophisticated time-stamping and synchronization options are supported by dual SMA connectors for interfacing to 1-PPS or 10-MHz reference clocks, in addition to the tunable on-board high accuracy, temperature compensated oscillator (TCXO). A comprehensive Board Management Controller (BMC) with host software support for advanced system monitoring is also provided.

The A5PS features and specifications include:

  • Altera Arria V GZ FPGA
  • PCIe x8 interface supporting Gen1, Gen2, or Gen3
  • Dual SFP+ cages for 2x 10GigE: Support for a wide range of optical transceiver; built-in low-latency active drivers/receivers for passive copper cables up to 7 m
  • Memory options (pick one): DDR3 (single 72-bit bank of up to 8 GBytes DDR3-1600 with ECC); QDRII+ (two 18-bit banks of up to 144 Mb each—288 Mb or 36 MB total)
  • Board Management Controller for Intelligent Platform Management
  • USB 2.0 for programming, debug, or control
  • Timestamping and synchronization support
    • Dual SMA for reference clock/synchronization inputs
    • Tunable high-accuracy TCXO
    • Programmable clock synthesizer (Si5338)
  • Complete software support with BittWare’s BittWorks II Toolkit
  • Broad range of IP offerings
    • 10 GigE MAC
    • TCP/IP Offload Engines (TOE), UDP Offload Engines
    • PTP/IEEE-1588
    • PCIe DMA

The A5PS board currently costs $1,500 in 1000s for the A5PS with the Arria V GZ E1 with no external memory. Contact BittWare for additional configurations, pricing, and details.

Source: BittWare


RTG4 Radiation-Tolerant FPGAs for High-speed Signal Processing Applications

Microsemi Corp. today announced availability of its RTG4 high-speed, signal-processing radiation-tolerant FPGA family. The RTG4’s reprogrammable flash technology offers complete immunity to radiation-induced configuration upsets in the harshest radiation environments, requiring no configuration scrubbing, unlike SRAM FPGA technology. RTG4 supports space applications requiring up to 150,000 logic elements and up to 300 MHz of system performance.Microsemi RTG4-  3-4view

Typical uses for RTG4 include remote sensing space payloads, such as radar, imaging and spectrometry in civilian, scientific and commercial applications. These applications span across weather forecasting and climate research, land use, astronomy and astrophysics, planetary exploration, and earth sciences. Other applications include mobile satellite services (MSS) communication satellites, as well as high altitude aviation, medical electronics and civilian nuclear power plant control. Such applications have historically used expensive radiation-hardened ASICs, which force development programs to incur substantial cost and schedule risk. RTG4 allows programs to access the ease-of-use and flexibility of FPGAs without sacrificing reliability or performance.

The flexibility, reliability and performance of RTG4 FPGAs make it much easier to achieve this. RTG4 is Microsemi’s latest development in a long history of radiation-tolerant FPGAs that are found in many NASA and international space programs.

Key product features include:

  • Up to 150,000 logic elements; each includes a four-input combinatorial look-up table (LUT4) and a flip-flop with built-in single event upset (SEU) and single event transient (SET) mitigation
  • High system performance, up to 300 MHz
  • 24 serial transceivers, with operation from 1 Gbps to 3.125 Gbps
  • 16 SEU- and SET-protected SpaceWire clock and data recovery circuits
  • 462 SEU- and SET-protected multiply-accumulate mathblocks
  • More than 5 Mb of on-board SEU-protected SRAM
  • Single event latch-up (SEL) and configuration memory upset immunity
  • Total ionizing dose (TID) beyond 100 Krad

Engineering silicon, Libero SoC development software, and RTG4 development kits are available now. RTG4 FPGAs and development kits have already shipped to some of the 120+ customers engaged in the RTG4 lead customer program. Flight units qualified to MIL-STD-883 Class B are expected to be available in early 2016.

Microsemi will present more information on RTG4 FPGAs in a live webinar on May 6 and will also be hosting Microsemi Space Forum events in the U.S., India and Europe starting in June, presenting information on RTG4 FPGAs and the extensive range of Microsemi space products.

Source: Microsemi Corp.

SoC FPGA Development Kit for Audio & Processing Applications

Coveloz recently announced the availability of its Pro Audio Ethernet AVB FPGA Development Kit, which is a ready-to-play platform for building scalable, cost-effective networked audio and processing applications built on modular hardware.Covelozpro-audio-dev-kit

Coveloz introduced its Networked Pro Audio SoC FPGA Development Kit during the Integrated System Europe (ISE) show in Amsterdam. According to the company, the new platform will enable manufacturers to achieve faster AVnu certification for new AVB solutions, creating an ideal development environment for live sound, conferencing systems, public address, audio post production, music creation, automotive infotainment and ADAS applications.

At the heart of the Coveloz development platform is a highly integrated System-on-Module (SOM), featuring an Altera Cyclone V SoC FPGA, which includes a dual-core ARM A9 processor, DDR3 memory and a large FPGA fabric, all in a low cost and compact package. The kit includes a multitude of networking and audio interfaces, including three Gigabit Ethernet ports as well as I2S, AES10/MADI, AES3/EBU and TDM audio.

Coveloz provides FPGA and Linux firmware enabling designers to quickly build AVnu Certified products for the broadcast, pro-audio/video and automotive markets. The platform is aimed at time-synchronized networks and includes grandmaster, PPS and word clock inputs and outputs as well as high quality timing references.

The Coveloz development kit is also host to the BACH-SOC platform, which integrates AES67 and Ethernet AVB audio networking and processing. Both SoC and PCIe-based FPGA implementations are available.

The Coveloz Bach Module is a full-featured and programmable audio networking and processing solution for easily integrating industry-standard AES67 and/or Ethernet AVB/TSN networking into audio/video distribution and processing products. The solution enables products with over 128+128 channels of digital streaming and 32-bit audio processing at 48, 96, or 192 kHz.

Supporting a wide range of interfaces, Coveloz complements the development platform with a comprehensive software toolkit and engineering services to help manufacturers reducing time to market. Coveloz also provides application examples to demonstrate the capabilities of the BACH-SOC platform.

The programmable BACH-SOC can be customized to a particular application in many ways—for instance, from selecting the number and type of audio interface to choosing audio processing alone, transport alone, or a combination.

Source: Coveloz

Synchronous Buck Regulator with Output Tracking and Sequencing for FPGAs and Microprocessors

Intersil Corp. recently announced the availability of the ISL8002B synchronous buck (step-down) switching regulator, which delivers up to 2 A of continuous output current from a 2.7- to 5.5-V input supply. Its 2-MHz switching frequency provides superior transient response, and its key features—including programmable soft-start and output tracking and sequencing of FPGAs and microprocessors—increase system reliability for point-of load conversions in networking, factory automation, instrumentation, and medical equipment.Intersil ISL8002B

The ISL8002B enables greater system reliability through several innovative features. For example, the regulator’s output tracking and sequencing of FPGAs and MPUs ensures sensitive multi-rails properly start up and shutdown. In addition, its output rails are configurable for coincidental, ratio metric, or sequential settings, ensuring the FPGA or MPU’s internal ESD diodes are not biased or overstressed during rising or falling outputs. The ISL8002B’s undervoltage lockout and several other protection/stability features protect the system from damage from unwanted electrical fault events. And its unique negative current protection prevents switch failure.

The ISL8002B’s superior transient response and high level of integration enable a complete synchronous step-down DC/DC converter solution in less than a 0.10 in2 footprint. By integrating low RDS(ON) high-side PMOS and low-side NMOS MOSFETs, the buck regulator eliminates the need for a bootstrap capacitor and diode. Its high efficiency enables the use of small inductors to further reduce board space.

Features and specifications:

  • Dimensions: 2 mm × 2 mm
  • Output tracking and sequencing
  • Switching at high frequency, 2 MHz
  • High peak efficiency: up to 95%
  • Wide input voltage range: 2.7 to 5.5 V
  • Maximum output current: 2A
  • Under voltage lockout, overvoltage protection
  • Selectable PFM or PWM operation
  • Over current, short-circuit protection
  • Over temperature/thermal protection

The ISL8002B synchronous buck regulator is available in a 2 mm  × 2 mm, eight-pin TDFN package. It costs $1 in 1,000-piece quantities. The ISL8002B DEMO1Z demonstration board is available for $23.

Source: Intersil Corp.



Quad Channel DPWM Step-Down Controller

Exar Corp. has introduced the XR77128, a universal PMIC that drives up to four independently controlled external DrMOS power stages at currents greater than 40 A for the latest 64-bit ARM processors, FPGAs, DSPs and ASICs. DrMOS technology is quickly growing in popularity in telecom and networking applications. These same applications find value in Exar’s Programmable Power technology which allows low component count, rapid development, easy system integration, dynamic control and telemetry. Depending on output current requirements, each output can be independently configured to directly drive external MOSFETs or DrMOS power stages.EX045_XR77128

The XR77128 is quickly configured to power nearly any FPGA, SoC, or DSP system through the use of Exar’s design tool, PowerArchitect, and programmed through an I²C-based SMBus compliant serial interface. It can also monitor and dynamically control and configure the power system through the same I²C interface. Five configurable GPIOs allow for fast system integration for fault reporting and status or for sequencing control.  A new Arduino-based development platform allows software engineers to begin code development for telemetry and dynamic control long before their hardware is available.

The XR77128 is available in a RoHS-compliant, green/halogen free space-saving 7 mm × 7 mm TQFN. It costs $7.75 in 1000-piece quantities.

Source: Exar Corp.

Industry’s Smallest Dual 3A/Single 6A Step-Down Power Module

Intersil Corp. recently announced the ISL8203M, a dual 3A/single 6A step-down DC/DC power module that simplifies power supply design for FPGAs, ASICs, microprocessors, DSPs, and other point of load conversions in communications, test and measurement, and industrial systems. The module’s compact 9.0 mm × 6.5 mm × 1.83 mm footprint combined with industry-leading 95% efficiency provides power system designers with a high-performance, easy-to-use solution for low-power, low-voltage applications.INT0325_ISL8203M_Intersil_Power_Module The ISL8203M is a complete power system in an encapsulated module that includes a PWM controller, synchronous switching MOSFETs, inductors and passive components to build a power supply supporting an input voltage range of 2.85 to 6 V. With an adjustable output voltage between 0.8 and 5 V, you can use one device to build a single 6-A or dual output 3-A power supply.

Designed to maximize efficiency, the ISL8203M power module offers best-in-class 15° C/W thermal performance and delivers 6 A at 85°C without the need for heatsinks or a fan. The ISL8203M leverages Intersil’s patented technology and advanced packaging techniques to deliver high power density and the best thermal performance in the industry, allowing the ISL8203M to operate at full load over a wide temperature range. The power module also provides over-temperature, over-current and under-voltage lockout protection, further enhancing its robustness and reliability.

Features and specifications:
•       Dual 3-A or single 6-A switching power supply
•       High efficiency, up to 95°
•       Wide input voltage range: 2.85 to 6 V
•       Adjustable output range: 0.8 to 5 V
•       Internal digital soft-start: 1.5 ms
•       External synchronization up to 4 MHz
•       Overcurrent protection

The ISL8203M power module is available in a 9 mm × 6.5 mm, QFN package. It costs $5.97 in 1,000-piece quantities. The ISL8203MEVAL2Z evaluation costs $67.

Source: Intersil

Impedance Matching Matters (EE Tip #145)

RF designers, as well as more and more digital-oriented designers, are used to thinking about impedance matching. But it is very easy to forget it when you are designing a non-RF project. A non-matched circuit will generate power losses as well as nasty reflection phenomena. (Refer to my article, “TDR Experiments,” Circuit Cellar 225, 2009.)

Impedance matching must be managed at the schematic stage, for example, by adding provisional matching pads for all integrated antennas, which will enable you to correct a slightly mis-adapted antenna (see Figure 1).

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Figure 1: Impedance matching requirements must be anticipated. In particular, any embedded antenna will surely need manual matching for optimal performance. If you forget to include some area for a matching network like this one on your PCB, you won’t achieve the best performance.

Impedance matching is also a PCB design issue. As rule of thumb, you can’t avoid impedance-matched tracks when you are working with frequencies higher than the speed of light divided by 10 times the board size. A typical 10-cm board would translate to a cutoff frequency of 300 MHz. A digital designer would then say: “Cool, my clock is only 100 MHz. No problem!” But a 100-MHz square-ware clock or digital signal means harmonic frequencies in the gigahertz range, so it would be wise to show some concern.

The problem could also happen with very slow clocks when you’re using fast devices. Do you want an example? Last year, one of my colleagues developed a complex system with plenty of large and fast FPGAs. These chips were programmed through a common JTAG link and we ended up with nasty problems on the JTAG bus. We still had issues even when we slowed down the JTAG speed to 100 kHz. So, it couldn’t have been an impedance matching problem, right? Wrong. It was. Simply because the JTAG is managed by the FPGA with the same ultra-fast logic cells that manage your fast logic so with stratospheric skew rates which translated into very fast transitions on the JTAG lines. This generated ringing due to improper impedance matching, so there were false transitions on the bus. Such a problem was easy to solve once we pinpointed it, but we lost some days in between.—Robert Lacoste, CC25, 2013


SmartFusion2 Advanced Dev Kit

Microsemi Corp. has announced a new larges-density, low-power SmartFusion2 150K LE SoC FPGA Advanced Development Kit. It’s meant for board-level designers and system architects who need to rapidly create system-level designs.

Source: Microsemi Corp.

Source: Microsemi Corp.

The kit’s features include:

  • Largest 150K LE development device
  • 2x FMC connectors (HPC and LPC)
  • Purchase of kits comes with a free one-year Libero SoC design software platinum license (valued at $2,500)
  • DDR3, SPI flash
  • 2× Gigabit Ethernet connectors
  • SMA connectors
  • PCIe x4 edge connector
  • Power measurement test points

Source: Microsemi


Q&A: Electrical Engineer & FPGA Enthusiast

Chris Zeh is a San Jose, CA-based hardware design engineer who enjoys working with FPGA development boards, application-specific integrated circuits, and logic analyzers. He recently told us about the projects he is involved with at STMicroelectronics and explained what he’s working on in his free time.

CIRCUIT CELLAR: Tell us about Idle-Logic.com. Why and when did you decide to start a blog?

ZehCHRIS: I started blogging in the winter of 2009, a little more than a year after I graduated Colorado State University with a BSEE. I realized that after graduating it was important to continue working on various projects to keep my mind and skills sharp. I figured the best way to chronicle and show off my projects was to start a blog—my little corner of the Internet.

CIRCUIT CELLAR: What types of projects do you feature on your site?

CHRIS: I like working on a wide range of different types of projects, varying from software development to digital and analog design. I’ve found that most of my projects highlighted on Idle-Logic.com have been ones focusing on FPGAs. I find these little reprogrammable, multipurpose ICs both immensely powerful and fascinating to work with.

My initial plan for the blog was to start a development project to create an FPGA equivalent to the Arduino. I wanted to build a main board with all the basic hardware to run an Altera Cyclone II FPGA and then create add-on PCBs with various sensors and interfaces. My main FPGA board was to be named the Saturn board, and the subsequent add-on “wings” were to be named after the various moons of Saturn.

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

The project proceeded nicely. I spent some time brushing up on my Photoshop skills to put together a logo and came up with a minimized BOM solution to provide power to the nine different voltage supplies, both linear regulators and switched-mode supplies. One aspect of FPGAs that can make them costly for hobbyist is that the programming JTAG cable was on the order of $300. Fortunately, there are a few more affordable off-brand versions, which I used at first. After many weeks of work, I finally had the total solution for the main FPGA board. The total cost of the prototype system was about $150. Eventually I came up with a way to bit bang the FPGA’s programming bitstream using a simple $15 USB-to-UART IC breakout board driven by a tiny Python application, eliminating the need for the pricey cable. This Future Technology Devices International FT232RL USB-to-UART IC also provided a clock output enabling me to further reduce the component count.

The project was a success in that I was compelled to completely digest the FPGA’s 470-page handbook, giving me a solid grasp of how to work with FPGAs such as the Cyclone II. The project was a failure in that the FPGA breakout board I wanted to use for the project was discontinued by the manufacturer. Creating and fabricating my own four-layer board and hand soldering the 208-pin package was both prohibitively expensive and also a little daunting.

Fortunately, at that time Terasic Technologies introduced its DE0-Nano, a $79 commercial, $59 academic, feature-packed FPGA evaluation board. The board comes with two 40-pin general I/O plus power headers, which has become a perfect alternative base platform for FPGA development. I now intend to develop add-on “wings” to work with this evaluation board.

CIRCUIT CELLAR: Tell us more about how you’ve been using Terasic Technologies’s DE0-Nano development and education board.

CHRIS: The main project I’ve been working on lately with the DE0-Nano is creating and adding support for a full-color 4.3” (480 × 272 pixel) thin- film transistor (TFT) touchscreen LCD. Because of the large pin count available and reconfigurable logic, the DE0-Nano can easily support the display. I used a Waveshare Electronics $20 display, which includes a 40-pin header that is almost but not quite compatible with the DE0-Nano’s 40-pin header. Using a 40-pin IDC gray cable, I was able to do some creative rewiring (cutting and swapping eight or so pins) to enable the two to mate with minimal effort. Eventually, once all the features are tested, I’ll fabricate a PCB in place of the cable.

There are many libraries available to drive the display, but for this project I want to develop the hardware accelerators and video pipeline from the ground up, purely though digital logic in the FPGA. I recently picked up an SD card breakout board and a small camera breakout board. Using these I would like to start playing around with image processing and object recognition algorithms.

CIRCUIT CELLAR: What do you do at STMicroelectronics and what types of projects are you working on?

CHRIS: My official title is Senior Hardware Design Engineer. This title mainly comes thanks to the first project I worked on for the company, which is ongoing—an FPGA-based serial port capture and decoding tool named the HyperSniffer. However, my main role is that of an application engineer.

I spend most of my time testing and debugging our prototype mixed-signal ASICs prior to mass production. These ASICs are built for the hard disk drive industry. They provide several switch-mode power supplies, linear regulators, brushless DC motor controllers, voice coil motor actuation, and a shock sensor digital processing chain, along with the various DACs, ADCs, and monitoring circuits all integrated into a single IC.

Our ASIC’s huge feature set requires me to stay sharp on a wide variety of topics, both analog and digital. A typical day has me down in the lab writing scripts in Python or Visual Studio, creating stimuli, and taking measurements using my 1-GHz, 10-GSPS LeCroy WavePro 7100A oscilloscope, several 6.5-digit multimeters, dynamic signal analyzers, and noise injection power supplies among other instruments. I work closely with our international design team and our customers to help discover and document bugs and streamline the system integration.

A few years back I was able to join my colleagues in writing “Power Electronics Control to Reduce Hard Disk Drive Acoustics Pure Tones,” an Institute of Electrical and Electronics Engineers (IEEE) paper published for the Control and Modeling for Power Electronics (COMPEL) 2010 conference. I presented the paper, poster, and demonstration at the conference discussing a novel technique to reduce acoustic noise generated by a spindle motor.

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent Himpe and Albino Miglialo.)

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent
Himpe and Albino Miglialo.)

CIRCUIT CELLAR: Tell us more about the HyperSniffer project.

CHRIS: The HyperSniffer project is an FPGA- based digital design project I first created right out of college. (My colleagues Vincent Himpe and Albino Miglialo did the board design and layout.) The tool is basically an application-specific logic analyzer. It enables us to help our customers troubleshoot problems that arise from serial port transmissions between their system-on-a-chip (SoC) and our ASIC. Through various triggering options it can collect and decode the two or three wire data transmissions, store them on on- board memory, and wait for retrieval and further processing by the application running on the PC. One of this tool’s nice features is that it is capable of synchronizing and communicating with an oscilloscope, enabling us to track down problems that happen in the analog domain that arise due to commands sent digitally.

You can read the entire interview in Circuit Cellar 290 (September 2014).

DE0-Nano Cyclone FPGA Development Board

With a DE0-Nano Cyclone FPGA Development Board, you can create your own sophisticated hardware using programmable logic. The development board includes an Altera Cyclone IV and additional components to connect and test hardware designs. It comes a pre-wired Cyclone IV FPGA for programming and connection to internal or external devices and circuit.

Source: Parallax

Source: Parallax

With the board, you can create sophisticated logic hardware fairly quickly using a hardware description language. Possible applications include dedicated digital logic processors, robotics, and DIY autonomous systems.

Source: Parallax