Active ESD Protection for Microcontrollers (EE Tip #129)

Microcontrollers need to be protected from of electrostatic discharge (ESD). You can use the circuit described in this post when you have an application requires a greater degree of ESD protection than what you get from an IC on its I/O pins. Although there are many ESD clamping devices out there, they don’t typically enable you to precisely limit voltage overshoots and undershoots.

Normally, when dealing with a microcontroller or other digital circuit the connections on the device are protected against electrostatic dis­charge. Nevertheless engineers are 4ever taking special precautions when handling such devices to avoid the risks of ESD: the lab will have an anti-static covering on the floor, and nylon clothes and shoes with soles made of insulating material are avoided. And, in case that is not enough, it is normal to wear an anti-static wrist band when moving devices from their anti-static bags to the anti-static bench surface. But what exactly do we mean when we talk about ESD?

HUMAN BODY MODEL

The first model for static discharge, mentioned as early as the 19thcentury, was the “human body model” (HBM). This takes as its starting point a voltage of up to 40 kV, a body capaci­tance of a few hundred picofarads, and a (skin) resistance of 1.5 kΩ. We find that even with a static voltage of only 10 kV, as might easily be acquired by walking across an artificial fiber car­pet in shoes with synthetic soles, it is possible to discharge through a fingertip at peak cur­rents of up to 20 A! The discharge also hap­pens in a very short period, perhaps measured in nanoseconds.

The HBM was adopted in the electronics industry in the 1970s with the introduction of sensitive JFET devices in space applications. The compo­nents were tested using a simple RC circuit like the one shown in Figure 1. The discharge cur­rent depends only on the resistance in the cir­cuit, and the damped discharge curve is largely free of oscillation and is accurately reproducible.

Figure 1—Standard test circuit and current waveform for the human body model

Figure 1—Standard test circuit and current waveform for the human body model

There are also other models that deal with dis­charge through a sensitive component, for exam­ple when a low-resistance electrical connection is made between two devices (the “machine model,” or MM), or when a static charge present on the device itself is discharged (the “charged device model,” or CDM)…

ESD CLAMP CIRCUITS

Figure 2 shows the typical protection circuitry provided on a microcontroller’s I/O port. This example is from an Atmel ATmega. Other microcontrol­lers and logic devices use similar arrangements. Two bipolar protection diodes conduct discharge currents that could cause undershoots or overshoots to one of the supply rails, either VCC or ground. However, the diodes take about 6 ns before they conduct fully.

Figure 2—Typical ESD protection circuit, as found in an Atmel microcontroller

Figure 2—Typical ESD protection circuit, as found in an Atmel microcontroller

Since ESD transients can sometimes be considerably shorter than this, it is possible that the CMOS circuit structures will be damaged long before the diodes spring into action. The parasitic capacitance of the pin is around 6 pF, and this is quickly charged up by the energy in the electrostatic discharge. Unfortunately, we cannot increase this capacitance with­out increasing the impedance of the pin, which is not desirable.

Standard ESD protection circuits like this one are designed to meet the particular requirements set by the ESD Association. However, it is becoming apparent that the traditional models are not appropriate for modern applications. Recent efforts have been directed toward developing a new “system level model” (SLM), which takes into account the different aspects of the older models. This model employs two stored charges that are discharged in different ways, creating a high-amplitude current pulse that decays very quickly plus a low-amplitude pulse that dies away more slowly. The energy transferred in a dis­charge under the SLM can be very much higher than that in the traditional models (Figure 3).

Figure 3—Current waveform under the system-level model

Figure 3—Current waveform under the system-level model

It is readily apparent that the conventional I/O pin circuitry on the IC is not sufficient to provide ESD protection under this model. Also, the con­tinuing industry pressure to make smaller and more complex structures makes it very difficult for design engineers even to maintain current levels of ESD protection, let alone improve on them. In other words: the silicon area needed to provide ESD protection in accordance with the SLM is simply not available! For this reason, external ESD clamp circuits are becoming more rele­vant. If a component provides only a low level of ESD protection (or even none at all) it is possible to add such a circuit at the points most at risk. The clamp circuits usually use so-called transient suppression diodes (transils or tranzorbs) which, like Zener diodes, start to conduct at a specified threshold voltage. However, unlike Zener diodes, they react quickly and can withstand much higher current transients. There are many variations on the circuit design, but none has exceptional performance and none offers precise clamping of voltage undershoots and overshoots.

STATE-OF-THE-ART ESD CLAMPING

If we are in the lucky position of not having to worry about the last cent of materials cost or the last square millimeter of board area, we can easily cre­ate a state-of-the-art active ESD protection circuit from discrete components (Figure 4).

Figure 4—This protection circuit clamps voltage transients outside defined upper and lower thresholds

Figure 4—This protection circuit clamps voltage transients outside defined upper and lower thresholds

The transistor circuit forms a kind of regulated voltage divider. The current through the two resistors R2 and R3 is such that the voltages across them are just enough that transistors T1 and T4 start to conduct and T2 and T3 are just short of saturation. So we have one base-emitter voltage (about 600 mV) across each of these two resistors, which means in turn that the emitters of T2 and T3 are 600 mV below VCC and above ground respectively. The circuit as shown is suitable for a 5 V supply; R1 can be changed to suit supplies of 3.3 V or 2.7 V if needed.

What is the point of this complexity? If the I/O pin is high (at +5 V) the upper 1N4148 switching diode will conduct fully as its cathode is at only 4.4 V. If a positive voltage transient should occur it will be conducted by the 1N4148, without switching delay, to the positive rail by 1N5817 Schottky diode D2, which acts quickly and has a low forward voltage. The same thing happens with polarities reversed when a negative voltage transient (below ground) occurs. Hence the digital inputs and outputs are protected against voltage excursions outside the range of the supply rails. In addition, voltage peaks are limited by the use of suppression inductors. The Murata BLM series inductor presents a relatively high impedance to signals in the 100 MHz range and so can significantly reduce the level of transients.

Although the approach we have described works well with digital levels, it is not suitable for use with signals destined for the analog-to-digital converter (ADC) on a microcontroller. In this case a reverse-biased diode between the signal and each supply rail is required to clamp overshoots and undershoots, with a pair of 10 kΩ series resistors to limit the transient current.

The series-connected capacitors C2 and C3 present a low-impedance path for transients between VCC and ground, and hence spikes on the supply rails will also be conducted away.—P. Kruger, “Active ESD Protection,” Elektor January/February 2014

Editor’s note: This article originally appeared in Elektor January/February 2014. It was shortened and updated for publication on CircuitCellar.com, which is an Elektor International Media Publication.

 

RESOURCES

www.teseq.de/de/de/service_support/technical_information/01_Transient_ immunity_testing_e.pdf

www.ti.com/lit/sg/sszb130b/sszb130b.pdf

www.semtech.com/circuit-protection/esd-protection/

www.murata.com/products/emc/basic/feature/bl_intro.html

Prevent Embedded Design Errors (CC 25th Anniversary Preview)

Attention, electrical engineers and programmers! Our upcoming 25th Anniversary Issue (available in early 2013) isn’t solely a look back at the history of this publication. Sure, we cover a bit of history. But the issue also features design tips, projects, interviews, and essays on topics ranging from user interface (UI) tips for designers to the future of small RAM devices, FPGAs, and 8-bit chips.

Circuit Cellar’s 25th Anniversary issue … coming in early 2013

Circuit Cellar columnist Robert Lacoste is one of the engineers whose essay will focus on present-day design tips. He explains that electrical engineering projects such as mixed-signal designs can be tedious, tricky, and exhausting. In his essay, Lacoste details 25 errors that once made will surely complicate (at best) or ruin (at worst) an embedded design project. Below are some examples and tips.

Thinking about bringing an electronics design to market? Lacoste highlights a common error many designers make.

Error 3: Not Anticipating Regulatory Constraints

Another common error is forgetting to plan for regulatory requirements from day one. Unless you’re working on a prototype that won’t ever leave your lab, there is a high probability that you will need to comply with some regulations. FCC and CE are the most common, but you’ll also find local regulations as well as product-class requirements for a broad range of products, from toys to safety devices to motor-based machines. (Refer to my article, “CE Marking in a Nutshell,” in Circuit Cellar 257 for more information.)

Let’s say you design a wireless gizmo with the U.S. market and later find that your customers want to use it in Europe. This means you lose years of work, as well as profits, because you overlooked your customers’ needs and the regulations in place in different locals.

When designing a wireless gizmo that will be used outside the U.S., having adequate information from the start will help you make good decisions. An example would be selecting a worldwide-enabled band like the ubiquitous 2.4 GHz. Similarly, don’t forget that EMC/ESD regulations require that nearly all inputs and outputs should be protected against surge transients. If you forget this, your beautiful, expensive prototype may not survive its first day at the test lab.

Watch out for errors

Here’s another common error that could derail a project. Lacoste writes:

Error 10: You Order Only One Set of Parts Before PCB Design

I love this one because I’ve done it plenty of times even though I knew the risk.

Let’s say you design your schematic, route your PCB, manufacture or order the PCB, and then order the parts to populate it. But soon thereafter you discover one of the following situations: You find that some of the required parts aren’t available. (Perhaps no distributor has them. Or maybe they’re available but you must make a minimum order of 10,000 parts and wait six months.) You learn the parts are tagged as obsolete by its manufacturer, which may not be known in advance especially if you are a small customer.

If you are serious about efficiency, you won’t have this problem because you’ll order the required parts for your prototypes in advance. But even then you might have the same issue when you need to order components for the first production batch. This one is tricky to solve, but only two solutions work. Either use only very common parts that are widely available from several sources or early on buy enough parts for a couple of years of production. Unfortunately, the latter is the only reasonable option for certain components like LCDs.

Ok, how about one more? You’ll have to check out the Anniversary Issue for the list of the other 22 errors and tips. Lacoste writes:

Error 12: You Forget About Crosstalk Between Digital and Analog Signals

Full analog designs are rare, so you have probably some noisy digital signals around your sensor input or other low-noise analog lines. Of course, you know that you must separate them as much as possible, but you can be sure that you will forget it more than once.

Let’s consider a real-world example. Some years ago, my company designed a high-tech Hi-Fi audio device. It included an on-board I2C bus linking a remote user interface. Do you know what happened? Of course, we got some audible glitches on the loudspeaker every time there was an I2C transfer. We redesigned the PCB—moving tracks and adding plenty of grounded copper pour and vias between sensitive lines and the problem was resolved. Of course we lost some weeks in between. We knew the risk, but underestimated it because nothing is as sensitive as a pair of ears. Check twice and always put guard-grounded planes between sensitive tracks and noisy ones.

Circuit Cellar’s Circuit Cellar 25th Anniversary Issue will be available in early 2013. Stay tuned for more updates on the issue’s content.