Tag Archives: EQ

Issue 274: EQ Answers

Posted on by
Reply

The answers to the Circuit Cellar 274 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—What is wrong with the name “programmable unijunction transistor?”

Answer 1—Unlike the original unijunction transistor—which really does have just a single junction—the programmable unijunction transistor (PUT) is actually a four-layer device that has three junctions, much like a silicon-controlled rectifier (SCR).

 

Problem 2—Given a baseband channel with 3-kHz bandwidth and a 40-dB signal-to-noise ratio (SNR), what is the theoretical capacity of this channel in bits per second?

Answer 2—The impulse response of an ideal channel with exactly 3 kHz of bandwidth is a sinc (i.e., sin(x)/x) pulse in the time domain that has nulls that are 1/6,000 s apart. This means you could send a series of impulses through this channel at a 6,000 pulses per second rate. And, if you sampled at exactly the correct instants on the receiving end, you could recover the amplitudes of each of those pulses with no interference from the other pulses on either side of it.

However, a 40-dB signal-to-noise ratio implies that the noise power is 1/10,000 of the maximum signal power. In terms of distinguishing voltage or current levels, this means you can send at most sqrt(10,000) = 100 distinct levels through the channel before they start to overlap, making it impossible to separate one from another at the receiving end.

100 levels translates to log2100 = 6.64 binary bits of information. This means the total channel capacity is 3,9840 bits/s (i.e., 6,000 pulses/s × 6.64 bits/pulse).

This is the basis for the Shannon-Hartley channel capacity theorem.

 

Problem 3—In general, is it possible to determine whether a system is linear and time-invariant (LTI) by simply examining its input and output signals?

Answer 3—In general, given an input signal and an output signal, you might be able to definitively state that the system is not linear and time-invariant (LTI), but you’ll never be able to definitively state that it is, only that it might be.

The general technique is to use information in the input signal to see whether the output signal can be composed from the input features. Input signals (e.g., impulses and steps) are easist to analyze, but other signals can also be analyzed.

 

Problem 4—One particular system has this input signal:

Figure 1

The output is given by:

Figure 2

Is this system LTI?

Answer 4—In this example, the input is a rectangular pulse that can be analyzed as the superposition of two step functions that are separated in time, one positive-going and the other negative-going. This makes the analysis easy, since you can see the initial response to the first step function then determine whether the response following the second step is a linear combination of two copies of the first part of the response.

In this case, the response to the first step function at t = 0 is that the output starts rising linearly, also at t = 0. The second (negative) input step function occurs at t = 0.5, and if the system is LTI, you would expect the output to also change what it’s doing at that time. In fact, you would expect the output to level off at whatever value it had reached at that time, because the LTI response to the second step should be a negative-going linear ramp, which, when added to the original response, should cancel out.

However, this is not the output signal received, so this system is definitely not LTI.

Issue 266: EQ Answers

Posted on by

The answers to the Circuit Cellar 266 (July 2012) Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—What’s the key difference between infinite impulse response (IIR) and finite impulse response (FIR) digital filters?

Answer 1—An infinite impulse response (IIR) filter incorporates feedback in its datapath, which means that any particular input sample can affect the output for an indefinite (infinite) time into the future. In contrast, a finite impulse response (FIR) filter uses only feedforward in its datapath, which means that any given input sample can only affect the output for a time corresponding to the number of storage (delay) stages in the filter.

Problem 2—Does the fact that the finite resolution of digital arithmetic effectively truncates the impulse response of an IIR filter turn it into an FIR filter?

Answer 2—While it’s technically true that the impulse response of an IIR filter implemented, say, with fixed-point arithmetic is effectively finite, this has no real bearing on its classification in terms of either its design or application. It’s still an IIR filter for all practical purposes.

Problem 3—The following pseudocode represents an implementation of a single-pole low-pass IIR filter, using 16-bit input and output values and a 24-bit internal accumulator and a filter coefficient of 1/256:



  # The 32-bit accumulator holds 16 integer


  # and 16 fractional bits


  $acc = 0x00000000;




  # The input value is a 16-bit integer.


  $input = 0xFFFF;




  # Offset used for rounding the accumulator


  # to 24 bits.


  $offset = 0x80;




  while (1) {


    # acc = (255*acc + input)/256


    $acc -= ($acc >> 8);


    $acc += ($input << 8) + $offset;


    # limit acc to 24 bits


    $acc &= 0xFFFFFF00;


    # output is integer part of acc


    $output = $acc >> 16;


  }


An implementor of this filter complained that “the output never reaches 0xFFFF.” What was the flaw in his reasoning?


Answer 3—The accumulator in this filter eventually settles at the value 0xFFFE8100. If you simply take the upper 16 bits of this, then the output value appears to be 0xFFFE. But if you properly round the accumulator by adding 0×00008000 before dropping the LSBs, then the output value is the correct value of 0xFFFF.


Problem 4—The original implementor’s solution was to change the $offset value to 0xFF. Why did this work?


Answer 4—Changing the $offset value to 0xFF effectively adds a bias to each input sample, which averages out to 0x00007F00 in the accumulator. The effect of this is to add the required rounding offset to the accumulator so that truncating the LSBs to create the 16-bit output value comes up with the correct answer.


.


					

		
		
	


				
					
	

		

						
Issue 264: EQ Answers

			
						

				Posted on   by  			

			
					


				

			
The answers to the Circuit Cellar 264 (July) Engineering Quotient are now available. The problems and answers are listed below, along with a schematic.


Problem 1a—Is it possible to transmit on-off (DC) signals between two pieces of equipment in both directions simultaneously on the same wire, in much the same way that telephones do for audio?


Source: D. Tweed, CC264


Answer 1a—Why not? Hybrids work just as well at DC as they do for audio; you just need a receiver with balanced inputs, like an RS-422 buffer:


All resistors are the same value (e.g., 4,700 Ω) and the transmit driver needs to be a voltage source (low impedance).


If the transmitter switches between, say, 0 V and 5 V, the opposite receiver will see a voltage differential of 0 V and 2.5 V, respectively, while the local receiver will just see 0V.


For long lines, you’ll probably want to use lower resistances and you’ll want to limit the slew rate of the transmitter so that the receiver doesn’t produce glitches on the transitions of the local transmitter.


If the RS-422 receiver is replaced with an op-amp differential amplifier with a gain of 2, then any analog voltage transmitted by one end will be reproduced at the other end.


Problem 1b—But doesn’t a true hybrid use transformers, or at least some tricky transformer simulation with op amps to ensure the transmitted signal does not appear on the receive port?


Answer 1b—No. A hybrid is just a bridge circuit, with one arm of the bridge replaced by the line and the termination at the far end. The transmit signal is applied to two opposite corners of the bridge and the receive signal is taken from the other two corners.


In order to provide the Tx/Rx isolation, the bridge must be balanced, which in the example above, means that the lower resistor on each side must match the impedance of the line/far end combination. For DC and short lines, a simple resistor suffices. At audio frequencies and with the long unshielded twisted pairs used in telephony, a more complex matching impedance is required.


Transformers are used only because it’s the easiest way (and the only passive way) to get a balanced drive and/or receive signal — the transmit driver and receiver cannot share a ground. In order to mass produce phones that were dirt cheap, yet simple and reliable, the phone company figured out how to use a multi-winding transformer to provide the both the isolation and the balanced/unbalanced conversion in both directions, usually with a single resistor and capacitor to provide the line matching. As noted, modern electronic phones use active electronics to achieve the same things.


As always, the theory is simple, but the practical implementations can get complicated.


Problem 2a—The conventional way to calculate the magnitude (length) of a vector is to take the square root of the sum of the squares of its components. On small processors, this can be somewhat difficult (especially the square root operation), and various approximations are used instead.


One approximation that works surprisingly well for 2-D vectors and complex numbers is to take the absolute values of the two components, compare them, then add 1/3 of the smaller to the larger.


What is the maximum error using this method?


Answer 2a—If we restrict the discussion to unit vectors at various angles A, the x component is cos(A) and the y component is sin(A), and the correct magnitude is 1.


Furthermore, let’s concentrate on angles between 0 and 45° — then we know that both cos(A) and sin(A) are positive and that cos(A) > sin(A). (The absolute value and compare operations provide the symmetry that covers the rest of the unit circle.) The approximation then gives the result


Magnitude = cos(A) + sin(A)/3


Graphing this shows that this is most negative (0.943) at 45° and most positive (1.054) at approximately 18.4° (the actual angle is given by atan(1/3) —can you show why?). The peak error is therefore –5.7%, +5.4%.


Problem 2b—Is there a similar formula that gives even better results?


Answer 2b—Yes. One more multiplication operation gives a result that has less than 4% error:


Magnitude = 0.960433 × max(|x|, |y|) + 0.397826 × min(|x|, |y|)


This function is most negative at 0° and 45°, and most positive at 22.5°. The error is ± 3.96%. This form is well-suited to DSPs that have multiply-accumulate units. The two constants can be expressed as 62943/65536 and 26072/65536, respectively.


Contributor: David Tweed




					

		
		
	


				
					
	

		

						
Issue 262: EQ Answers

			
						

				Posted on   by  			

			
					


				

			
Problem 1—The classic two-transistor astable multivibrator is shown below. Typically, R2 and R3 have at least 10 times the value of R1 and R4. This circuit oscillates, with Q1 and Q2 turning on alternately. From the point in time in a cycle where Q1 first switches on, describe what happens until Q2 switches on.


Source: D. Tweed, CC262


Answer 1—Right before the moment Q1 switches on, C1 is charged to VCC – VBE, with its left end positive, and the left end of C2 has just reached +VBE. The right end of C2 is being held at VCE(SAT) by Q2.


Source: D. Tweed, CC262


So, as Q1 begins to switch on, it pulls the left end of C1 low, and this also pulls the right end of C1 low, cutting off Q2. This in turn allows the right end of C2 to rise, emphasizing the turn-on of Q1 by increasing the voltage (and current) at the base of Q1.


Once Q1 is fully on, the right end of C1 is now at VCE(SAT)– (VCC – VBE) (a fairly substantial negative voltage), and C1 now begins to charge in the other direction, through R2. Once the right end of C1 reaches +VBE, Q2 begins to turn on, starting the second half of the cycle.


Problem 2—What determines the time of one half-cycle of the oscillation? Does this depend on VCC?


Answer 2—The time of the half-cycle described previously is the time that it takes the right end of C1 to charge from –(VCC – (VBE + VCE(SAT))) to +VBE.


Now, keep in mind that the capacitor is charging “toward” +VCC, but it gets halted by the B-E junction of Q2 at +VBE. This charging is occuring at a rate determined by the time constant C1 × R2, and we’re basically interested in the time that it takes to move halfway from its starting value to its final value. This works out to –ln(0.5), or 0.693 times the R-C time constant.


As long as VCC >> VBE, the time does not depend on VCC. That isn’t to say, however, that VCC can be arbitrarily large. If it exceeds the reverse-breakdown voltage of the transistors’ B-E junctions, current will flow and perturb the timing.


Problem 3—Recently, a different circuit appeared on the web, shown below. Again, R2 and R3 are significantly larger than R1 and R4. The initial reaction of one observer was that this circuit can’t work, because there’s no DC bias path for either transistor. Is this assessment correct?


Source: D. Tweed, CC262


Answer 3—No, it isn’t. This circuit can oscillate just fine. Again, look at how C1 charges and discharges.


Source: D. Tweed, CC262


If C1 starts out discharged, it will charge through R1 and the B-E junction of Q2. This current will turn on Q2, holding its collector at ground (really VCE(SAT)) and preventing Q1 from turning on.


However, as C1 reaches full charge, the current through it decays below a level that will keep Q2 turned on. When it starts to turn off, its collector voltage rises, which also forces current into Q1′s base through C2. As Q1 begins to turn on, it pulls its collector low, which also pulls the base of Q2 lower, emphasizing its turn-off. The circuit quickly “snaps” to the other state, with Q1 on and Q2 off. C1 is discharged through Q1 and D2 at the same time that C2 begins charging through R4 and Q1′s B-E junction.


Problem 4—What role do R2 and R3 play in this circuit?


Answer 4—R2 and R3 never have more than ±VBE across them; as a result, the current through them is negligible relative to the current through the capacitors. In other words, they’re superfluous.


Question 5—Does the timing of this circuit depend on VCC? If not, what does it depend on?


Answer 5—The time from when one of the transistors turns on to when it turns off is determined by the currents flowing into its base and collector. When the current into the base drops below the value needed to sustain the current into the collector, the transistor begins to turn off, and the circuit feedback then insures that this happens quickly.


Looking at Q2, and ignoring the transient associated with discharging C2 for now, the collector current is set by R4. The initial base current is set by R1, but this decays exponentially with a time constant of R1 × C1.


Therefore, the primary determinant of the half-cycle time period (in addition to the R-C time constant) is the current transfer ratio, or hFE of each transistor. When the base current drops to a value of 1/hFE of the collector current, the transistor begins to turn off.


Since both currents scale in the same way with VCC, it has no direct effect on the timing. There is only a secondary effect if the value of hFE changes with the value of the collector current.


Contributor:  David Tweed


 


 


					

		
		
	


				
					
	

		

						
Issue 260: EQ Answers

			
						

				Posted on   by  			

			
					


				

			
These are the answers to the EQ questions that appeared in Circuit Cellar 260 (March 2012).


Problem 1—In an RS-232 interface, why is the idle or “mark” level a negative voltage?


Answer 1—RS-232 was developed in the days when people were connecting electromechanical teletypes to telephone lines with modems, and in fact, at that time the design of any equipment connected to a phone line was tightly controlled by the phone company.


The reason RS-232 uses a negative voltage for its idle state is the same reason the phone lines themselves use a negative voltage relative to ground for power—copper wires in long cables potentially exposed to moisture are significantly less likely to corrode if they have a negative DC bias on them.


Problem 2—Similarly, why does the “mark” level correspond to a logical “high” level on the TTL side of the interface?


Answer 2—Again, back in the days when RS-232 was developed, the primary logic families in use were DTL and TTL. Both of these technologies draw significantly less power when a signal is in the high state than in the low state, so the high state is preferred for the inactive state of any signal.


Problem 3—What does the following C function compute? You may assume the input argument is a positive integer.


Answer 3—Remember the algorithm that computes integer square roots by subtracting successive odd numbers from the input value? This function extends that concept to computing integer cube roots.


The reason this works is that taking the differences between successive values is the discrete equivalent of taking a derivative in the continuous world. The derivative of a cubic curve is a quadratic, and the derivative of a quadratic is a straight line. To generate a “straight line” in the discrete world, you just add a constant to a variable.


When you look at successive squares—0, 1, 4, 9, 16, 25, etc.—the differences are 1, 3, 5, 7, 9, etc. This is why the algorithm that subtracts odd numbers works for computing square roots.


When you look at the successive cubes—0, 1, 8, 27, 64, 125, etc.—the first set of differences is the sequence 1, 7, 19, 37, 61, etc. This doesn’t look very useful until you take the differences between those numbers, which are: 6, 12, 18, 24, etc., which is obviously another straight line.


Problem 4—Suppose you are given some calibration constants for a sensor in the form of four-digit hexadecimal (16-bit) integers, and you are told that the format of these numbers is “7 integer bits and 9 fractional bits.” How would you go about converting these constants to floating-point so that you could, for example, work with them in a spreadsheet?


Answer 4—The direct way to convert numbers in an arbitrary fixed-point representation to the equivalent floating-point value is to figure out what the representation for “1.000” would be in the fixed-point notation and then divide the given numbers by that constant.


In this case, with 7 integer bits and 9 fraction bits, “1.000” would be represented as binary 0000001.000000000, or 0×0200. So, if you are given a constant of, say, 0×5453, just divide it by 0×0200 to find out that it represents the value “42.162.”


Contributed by David Tweed (eq at circuitcellar.com)