Issue 274: EQ Answers

The answers to the Circuit Cellar 274 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—What is wrong with the name “programmable unijunction transistor?”

Answer 1—Unlike the original unijunction transistor—which really does have just a single junction—the programmable unijunction transistor (PUT) is actually a four-layer device that has three junctions, much like a silicon-controlled rectifier (SCR).

 

Problem 2—Given a baseband channel with 3-kHz bandwidth and a 40-dB signal-to-noise ratio (SNR), what is the theoretical capacity of this channel in bits per second?

Answer 2—The impulse response of an ideal channel with exactly 3 kHz of bandwidth is a sinc (i.e., sin(x)/x) pulse in the time domain that has nulls that are 1/6,000 s apart. This means you could send a series of impulses through this channel at a 6,000 pulses per second rate. And, if you sampled at exactly the correct instants on the receiving end, you could recover the amplitudes of each of those pulses with no interference from the other pulses on either side of it.

However, a 40-dB signal-to-noise ratio implies that the noise power is 1/10,000 of the maximum signal power. In terms of distinguishing voltage or current levels, this means you can send at most sqrt(10,000) = 100 distinct levels through the channel before they start to overlap, making it impossible to separate one from another at the receiving end.

100 levels translates to log2100 = 6.64 binary bits of information. This means the total channel capacity is 3,9840 bits/s (i.e., 6,000 pulses/s × 6.64 bits/pulse).

This is the basis for the Shannon-Hartley channel capacity theorem.

 

Problem 3—In general, is it possible to determine whether a system is linear and time-invariant (LTI) by simply examining its input and output signals?

Answer 3—In general, given an input signal and an output signal, you might be able to definitively state that the system is not linear and time-invariant (LTI), but you’ll never be able to definitively state that it is, only that it might be.

The general technique is to use information in the input signal to see whether the output signal can be composed from the input features. Input signals (e.g., impulses and steps) are easist to analyze, but other signals can also be analyzed.

 

Problem 4—One particular system has this input signal:

Figure 1

The output is given by:

Figure 2

Is this system LTI?

Answer 4—In this example, the input is a rectangular pulse that can be analyzed as the superposition of two step functions that are separated in time, one positive-going and the other negative-going. This makes the analysis easy, since you can see the initial response to the first step function then determine whether the response following the second step is a linear combination of two copies of the first part of the response.

In this case, the response to the first step function at t = 0 is that the output starts rising linearly, also at t = 0. The second (negative) input step function occurs at t = 0.5, and if the system is LTI, you would expect the output to also change what it’s doing at that time. In fact, you would expect the output to level off at whatever value it had reached at that time, because the LTI response to the second step should be a negative-going linear ramp, which, when added to the original response, should cancel out.

However, this is not the output signal received, so this system is definitely not LTI.

Issue 272: EQ Answers

The answers to the Circuit Cellar 272 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—Why does the power dissipation of a Darlington transistor tend to be higher than that of a single bipolar transistor in switching applications?

Answer 1—In switching applications, a single transistor can saturate, resulting in a low VCE of 0.3 to 0.4 V. However, in a Darlington pair, the output transistor is prevented from saturating by the negative feedback provided by the driver transistor. If the collector voltage drops below the sum of the VBE of the output transistor (about 0.7 V) and the VCE(sat) of the driver transistor (about 0.3 V), the drive current to the output transistor is reduced, preventing it from going into saturation itself. Therefore, the effective VCE(sat) of the Darlington pair is 1 V or more, resulting in much higher dissipation at a given current level.

Problem 2—Suppose you have some 3-bit data, say, grayscale values for which 000 = black and 111 = white. You have a display device that takes 8-bit data, and you want to extend the bit width of your data to match.

If you just pad the data with zeros, you get the value 11100000 for white, which is not full white for the 8-bit display—that would be 11111111. What can you do?

Answer 2—One clever trick is to repeat the bits you have as many times as necessary to fill the output field width. For example, if the 3-bit input value is ABC, the output value would be ABCABCAB. This produces the following mapping, which interpolates nicely between full black and full white (see Table 1). Note that this mapping preserves the original bits; if you want to go back to the 3-bit representation, just take the MSBs and you have the original data.

3-bit INPUT 8-bit OUTPUT
000 00000000
001 00100100
010 01001001
011 01101101
100 10010010
101 10110110
110 11011011
111 11111111

Problem 3—Can an induction motor (e.g., squirrel-cage type) be used as a generator?

Answer 3—Believe it or not, yes it can.

An induction motor has no electrical connections to the rotor; instead, a magnetic field is induced into the rotor by the stator. The motor runs slightly slower than “synchronous” speed—typically 1725 or 3450 rpm when on 60 Hz power.

If the motor is provided with a capacitive load, is driven at slightly higher than synchronous speed (1875 or 3750 rpm), and has enough residual magnetism in the rotor to get itself going, it will generate power up to approximately its rating as a motor. The reactive current of the load capacitor keeps the rotor energized in much the same way as when it is operating as a motor.

See www.qsl.net/ns8o/Induction_Generator.html for additional details.

Problem 4—In Figure 1, why does this reconstruction of a 20-kHz sinewave sampled at 44.1 kHz show ripple in its amplitude?

Answer 4—The actual sampled data, represented by the square dots in the diagram, contains equal levels of Fsignal (the sine wave) and Fsample-Fsignal (one of the aliases of the sinewave). Any reconstruction filter is going to have difficulty passing the one and eliminating the other, so you inevitably get some of the alias signal, which, when added to the desired signal, produces the “modulation” you see.

In the case of a software display of a waveform on a computer screen (e.g., such as you might see in software used to edit audio recordings), they’re probably using an FIR low-pass filter (sin(x)/x coefficients) windowed to some finite length. A shorter window gives faster drawing times, so they’re making a tradeoff between visual fidelity and interactive performance. The windowing makes the filter somewhat less than brick-wall, so you get the leakage of the alias and the modulation.

In the case of a real audio D/A converter, even with oversampling you can’t get perfect stopband attenuation (and you must always do at least some of the filtering in the analog domain), so once again you see the leakage and modulation.

In this example, Fsignal = 0.9×Fnyquist, so Falias = 1.1×Fnyquist and Falias/Fsignal = 1.22. To eliminate the visible artifacts, the reconstruction filter would need to have a slope of about 60dB over this frequency span, or about 200 dB/octave.

Issue 270: EQ Answers

The answers to the Circuit Cellar 270 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1: Given a microprocessor that has hardware support for just one level of priority for interrupts, is it possible to implement multiple priorities in software? If so, what are the prerequisites that are required?

Answer 1: Yes, given a few basic capabilities, it is possible to implement multiple levels of interrupt priority in software. The basic requirements are that it must be possible to reenable interrupts from within an interrupt service routine (ISR) and that the different interrupt sources can be individually masked.

Question 2: What is the basic scheme for implementing software interrupt priorities?

Answer 2: In normal operation, all the interrupt sources are enabled, along with the processor’s global-interrupt mask.

When an interrupt occurs, the global interrupt mask is disabled and the “master” ISR is entered. This code must (quickly) determine which interrupt occurred, disable that interrupt and all lower-priority interrupts at their sources, then reenable the global-interrupt mask before jumping to the ISR for that interrupt. This can often be facilitated by precomputing a table of interrupt masks for each priority level.

Question 3: What are some of the problems associated with software interrupt priorities?

Answer 3: For one thing, the start-up latency of all the ISRs is increased by the time spent in the “master” ISR. This can be a problem in time-critical systems. This scheme enables interrupts to be nested, so the stack must be large enough to handle the worst-case nesting of ISRs, on top of the worst-case nesting of non-interrupt subroutine calls.

Finally, it is very tricky to do this in anything other than Assembly language. If you want to use a high-level language, you’ll need to be intimately familiar with the language’s run-time library and how it handles interrupts and reentrancy, in general.

Answer 4: Yes, on most such processors, you can execute a subroutine call to a “return from interrupt” instruction while still in the master ISR, which will then return to the master ISR, but with interrupts enabled.

Check to see whether the “return from interrupt” affects any other processor state (e.g., popping a status word from the stack) and prepare the stack accordingly.

Also, beware that another interrupt could occur immediately thereafter, and make sure the master ISR is reentrant beyond that point.

 

Contributed by David Tweed

Issue 268: EQ Answers

Problem 1: A transformer’s windings, when measured individually (all other windings disconnected), have a certain amount of inductance. If you have a 1:1 transformer (both windings have the same inductance) and connect the windings in series, what value of inductance do you get?

Answer 1: Assuming you connect the windings in-phase, you’ll have double the number of turns, so the resulting inductance will be about four times the inductance of one winding alone.

If you hook them up out of phase, the inductance will cancel out and you’ll be left with the resistance of the wire and a lot of parasitic inter-winding capacitance.

Problem 2: If you connect the windings in parallel, what value of inductance do you get?

Answer 2: With the two windings connected in-phase and in parallel, the inductance will be exactly the same as the single-winding case. But the resulting inductor will be able to handle twice the current, as long as the core itself doesn’t saturate.

Question 3: Suppose you have a 32-bit word in your microprocessor, and you want to count how many contiguous strings ones that appear in it. For example, the word “01110001000111101100011100011111” contains six such strings. Can you come up with an algorithm that uses simple shifts, bitwise logical and arithmetic operators, but —here’s the twist—does not require iterating over each bit in the word?

Answer 3: Here’s a solution that iterates over the number of strings, rather than the number of bits in the word.

int nstrings (unsigned long int x)
{
   int result = 0;

   /* convert x into a word that has a '1' for every
    * transition from 0 to 1 or 1 to 0 in the original
    * word.
    */
   x ^= (x << 1);

   /* every pair of ones in the new word represents
    * a string of ones in the original word. Remove
    * them two at a time and keep count.
    */
   while (x) {
     /* remove the lowest set bit from x; this
      * represents the start of a string of ones.
      */
     x &= ~(x & -x);
     ++result;

     /* remove the next set bit from x; this
      * represents the end of that string of ones.
      */
     x &= ~(x & -x);
   }
   return result;
}

Problem 4: For the purpose of timing analysis, the operating conditions of an FPGA are sometimes known as “PVT,” which stands for “process, voltage, and temperature.” Voltage and temperature are pretty much self-explanatory, but what does process mean in this context?

Answer 4: The term process in this case refers to the manufacturing process at the plant where they make the FPGA. It’s a measure of the statistical variability of the physical characteristics from chip to chip as they come off the line.
This includes everything from mask alignment to etching times to doping levels. These things affect electrical parameters such as sheet and contact resistance, actual transistor gains, and thresholds and parasitic capacitances.
These kinds of variations are unavoidable, and the P in PVT is an attempt to account for their effects in the timing analysis. The idea is to make the analysis conservative enough so that your design will work reliably despite these variations.

Contributed by David Tweed

Issue 266: EQ Answers

The answers to the Circuit Cellar 266 (July 2012) Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—What’s the key difference between infinite impulse response (IIR) and finite impulse response (FIR) digital filters?

Answer 1—An infinite impulse response (IIR) filter incorporates feedback in its datapath, which means that any particular input sample can affect the output for an indefinite (infinite) time into the future. In contrast, a finite impulse response (FIR) filter uses only feedforward in its datapath, which means that any given input sample can only affect the output for a time corresponding to the number of storage (delay) stages in the filter.

Problem 2—Does the fact that the finite resolution of digital arithmetic effectively truncates the impulse response of an IIR filter turn it into an FIR filter?

Answer 2—While it’s technically true that the impulse response of an IIR filter implemented, say, with fixed-point arithmetic is effectively finite, this has no real bearing on its classification in terms of either its design or application. It’s still an IIR filter for all practical purposes.

Problem 3—The following pseudocode represents an implementation of a single-pole low-pass IIR filter, using 16-bit input and output values and a 24-bit internal accumulator and a filter coefficient of 1/256:


  # The 32-bit accumulator holds 16 integer
  # and 16 fractional bits
  $acc = 0x00000000;

  # The input value is a 16-bit integer.
  $input = 0xFFFF;

  # Offset used for rounding the accumulator
  # to 24 bits.
  $offset = 0x80;

  while (1) {
    # acc = (255*acc + input)/256
    $acc -= ($acc >> 8);
    $acc += ($input << 8) + $offset;
    # limit acc to 24 bits
    $acc &= 0xFFFFFF00;
    # output is integer part of acc
    $output = $acc >> 16;
  }

An implementor of this filter complained that “the output never reaches 0xFFFF.” What was the flaw in his reasoning?

Answer 3—The accumulator in this filter eventually settles at the value 0xFFFE8100. If you simply take the upper 16 bits of this, then the output value appears to be 0xFFFE. But if you properly round the accumulator by adding 0x00008000 before dropping the LSBs, then the output value is the correct value of 0xFFFF.

Problem 4—The original implementor’s solution was to change the $offset value to 0xFF. Why did this work?

Answer 4—Changing the $offset value to 0xFF effectively adds a bias to each input sample, which averages out to 0x00007F00 in the accumulator. The effect of this is to add the required rounding offset to the accumulator so that truncating the LSBs to create the 16-bit output value comes up with the correct answer.

.