Issue 270: EQ Answers

The answers to the Circuit Cellar 270 Engineering Quotient are now available. The problems and answers are listed below.

Problem 1: Given a microprocessor that has hardware support for just one level of priority for interrupts, is it possible to implement multiple priorities in software? If so, what are the prerequisites that are required?

Answer 1: Yes, given a few basic capabilities, it is possible to implement multiple levels of interrupt priority in software. The basic requirements are that it must be possible to reenable interrupts from within an interrupt service routine (ISR) and that the different interrupt sources can be individually masked.

Question 2: What is the basic scheme for implementing software interrupt priorities?

Answer 2: In normal operation, all the interrupt sources are enabled, along with the processor’s global-interrupt mask.

When an interrupt occurs, the global interrupt mask is disabled and the “master” ISR is entered. This code must (quickly) determine which interrupt occurred, disable that interrupt and all lower-priority interrupts at their sources, then reenable the global-interrupt mask before jumping to the ISR for that interrupt. This can often be facilitated by precomputing a table of interrupt masks for each priority level.

Question 3: What are some of the problems associated with software interrupt priorities?

Answer 3: For one thing, the start-up latency of all the ISRs is increased by the time spent in the “master” ISR. This can be a problem in time-critical systems. This scheme enables interrupts to be nested, so the stack must be large enough to handle the worst-case nesting of ISRs, on top of the worst-case nesting of non-interrupt subroutine calls.

Finally, it is very tricky to do this in anything other than Assembly language. If you want to use a high-level language, you’ll need to be intimately familiar with the language’s run-time library and how it handles interrupts and reentrancy, in general.

Answer 4: Yes, on most such processors, you can execute a subroutine call to a “return from interrupt” instruction while still in the master ISR, which will then return to the master ISR, but with interrupts enabled.

Check to see whether the “return from interrupt” affects any other processor state (e.g., popping a status word from the stack) and prepare the stack accordingly.

Also, beware that another interrupt could occur immediately thereafter, and make sure the master ISR is reentrant beyond that point.

 

Contributed by David Tweed

Issue 268: EQ Answers

Problem 1: A transformer’s windings, when measured individually (all other windings disconnected), have a certain amount of inductance. If you have a 1:1 transformer (both windings have the same inductance) and connect the windings in series, what value of inductance do you get?

Answer 1: Assuming you connect the windings in-phase, you’ll have double the number of turns, so the resulting inductance will be about four times the inductance of one winding alone.

If you hook them up out of phase, the inductance will cancel out and you’ll be left with the resistance of the wire and a lot of parasitic inter-winding capacitance.

Problem 2: If you connect the windings in parallel, what value of inductance do you get?

Answer 2: With the two windings connected in-phase and in parallel, the inductance will be exactly the same as the single-winding case. But the resulting inductor will be able to handle twice the current, as long as the core itself doesn’t saturate.

Question 3: Suppose you have a 32-bit word in your microprocessor, and you want to count how many contiguous strings ones that appear in it. For example, the word “01110001000111101100011100011111″ contains six such strings. Can you come up with an algorithm that uses simple shifts, bitwise logical and arithmetic operators, but —here’s the twist—does not require iterating over each bit in the word?

Answer 3: Here’s a solution that iterates over the number of strings, rather than the number of bits in the word.

int nstrings (unsigned long int x)
{
   int result = 0;

   /* convert x into a word that has a '1' for every
    * transition from 0 to 1 or 1 to 0 in the original
    * word.
    */
   x ^= (x << 1);

   /* every pair of ones in the new word represents
    * a string of ones in the original word. Remove
    * them two at a time and keep count.
    */
   while (x) {
     /* remove the lowest set bit from x; this
      * represents the start of a string of ones.
      */
     x &= ~(x & -x);
     ++result;

     /* remove the next set bit from x; this
      * represents the end of that string of ones.
      */
     x &= ~(x & -x);
   }
   return result;
}

Problem 4: For the purpose of timing analysis, the operating conditions of an FPGA are sometimes known as “PVT,” which stands for “process, voltage, and temperature.” Voltage and temperature are pretty much self-explanatory, but what does process mean in this context?

Answer 4: The term process in this case refers to the manufacturing process at the plant where they make the FPGA. It’s a measure of the statistical variability of the physical characteristics from chip to chip as they come off the line.
This includes everything from mask alignment to etching times to doping levels. These things affect electrical parameters such as sheet and contact resistance, actual transistor gains, and thresholds and parasitic capacitances.
These kinds of variations are unavoidable, and the P in PVT is an attempt to account for their effects in the timing analysis. The idea is to make the analysis conservative enough so that your design will work reliably despite these variations.

Contributed by David Tweed

Issue 266: EQ Answers

The answers to the Circuit Cellar 266 (July 2012) Engineering Quotient are now available. The problems and answers are listed below.

Problem 1—What’s the key difference between infinite impulse response (IIR) and finite impulse response (FIR) digital filters?

Answer 1—An infinite impulse response (IIR) filter incorporates feedback in its datapath, which means that any particular input sample can affect the output for an indefinite (infinite) time into the future. In contrast, a finite impulse response (FIR) filter uses only feedforward in its datapath, which means that any given input sample can only affect the output for a time corresponding to the number of storage (delay) stages in the filter.

Problem 2—Does the fact that the finite resolution of digital arithmetic effectively truncates the impulse response of an IIR filter turn it into an FIR filter?

Answer 2—While it’s technically true that the impulse response of an IIR filter implemented, say, with fixed-point arithmetic is effectively finite, this has no real bearing on its classification in terms of either its design or application. It’s still an IIR filter for all practical purposes.

Problem 3—The following pseudocode represents an implementation of a single-pole low-pass IIR filter, using 16-bit input and output values and a 24-bit internal accumulator and a filter coefficient of 1/256:


  # The 32-bit accumulator holds 16 integer
  # and 16 fractional bits
  $acc = 0x00000000;

  # The input value is a 16-bit integer.
  $input = 0xFFFF;

  # Offset used for rounding the accumulator
  # to 24 bits.
  $offset = 0x80;

  while (1) {
    # acc = (255*acc + input)/256
    $acc -= ($acc >> 8);
    $acc += ($input << 8) + $offset;
    # limit acc to 24 bits
    $acc &= 0xFFFFFF00;
    # output is integer part of acc
    $output = $acc >> 16;
  }

An implementor of this filter complained that “the output never reaches 0xFFFF.” What was the flaw in his reasoning?

Answer 3—The accumulator in this filter eventually settles at the value 0xFFFE8100. If you simply take the upper 16 bits of this, then the output value appears to be 0xFFFE. But if you properly round the accumulator by adding 0×00008000 before dropping the LSBs, then the output value is the correct value of 0xFFFF.

Problem 4—The original implementor’s solution was to change the $offset value to 0xFF. Why did this work?

Answer 4—Changing the $offset value to 0xFF effectively adds a bias to each input sample, which averages out to 0x00007F00 in the accumulator. The effect of this is to add the required rounding offset to the accumulator so that truncating the LSBs to create the 16-bit output value comes up with the correct answer.

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Issue 264: EQ Answers

The answers to the Circuit Cellar 264 (July) Engineering Quotient are now available. The problems and answers are listed below, along with a schematic.

Problem 1a—Is it possible to transmit on-off (DC) signals between two pieces of equipment in both directions simultaneously on the same wire, in much the same way that telephones do for audio?

Source: D. Tweed, CC264

Answer 1a—Why not? Hybrids work just as well at DC as they do for audio; you just need a receiver with balanced inputs, like an RS-422 buffer:

All resistors are the same value (e.g., 4,700 Ω) and the transmit driver needs to be a voltage source (low impedance).

If the transmitter switches between, say, 0 V and 5 V, the opposite receiver will see a voltage differential of 0 V and 2.5 V, respectively, while the local receiver will just see 0V.

For long lines, you’ll probably want to use lower resistances and you’ll want to limit the slew rate of the transmitter so that the receiver doesn’t produce glitches on the transitions of the local transmitter.

If the RS-422 receiver is replaced with an op-amp differential amplifier with a gain of 2, then any analog voltage transmitted by one end will be reproduced at the other end.

Problem 1b—But doesn’t a true hybrid use transformers, or at least some tricky transformer simulation with op amps to ensure the transmitted signal does not appear on the receive port?

Answer 1b—No. A hybrid is just a bridge circuit, with one arm of the bridge replaced by the line and the termination at the far end. The transmit signal is applied to two opposite corners of the bridge and the receive signal is taken from the other two corners.

In order to provide the Tx/Rx isolation, the bridge must be balanced, which in the example above, means that the lower resistor on each side must match the impedance of the line/far end combination. For DC and short lines, a simple resistor suffices. At audio frequencies and with the long unshielded twisted pairs used in telephony, a more complex matching impedance is required.

Transformers are used only because it’s the easiest way (and the only passive way) to get a balanced drive and/or receive signal — the transmit driver and receiver cannot share a ground. In order to mass produce phones that were dirt cheap, yet simple and reliable, the phone company figured out how to use a multi-winding transformer to provide the both the isolation and the balanced/unbalanced conversion in both directions, usually with a single resistor and capacitor to provide the line matching. As noted, modern electronic phones use active electronics to achieve the same things.

As always, the theory is simple, but the practical implementations can get complicated.

Problem 2a—The conventional way to calculate the magnitude (length) of a vector is to take the square root of the sum of the squares of its components. On small processors, this can be somewhat difficult (especially the square root operation), and various approximations are used instead.

One approximation that works surprisingly well for 2-D vectors and complex numbers is to take the absolute values of the two components, compare them, then add 1/3 of the smaller to the larger.

What is the maximum error using this method?

Answer 2a—If we restrict the discussion to unit vectors at various angles A, the x component is cos(A) and the y component is sin(A), and the correct magnitude is 1.

Furthermore, let’s concentrate on angles between 0 and 45° — then we know that both cos(A) and sin(A) are positive and that cos(A) > sin(A). (The absolute value and compare operations provide the symmetry that covers the rest of the unit circle.) The approximation then gives the result

Magnitude = cos(A) + sin(A)/3

Graphing this shows that this is most negative (0.943) at 45° and most positive (1.054) at approximately 18.4° (the actual angle is given by atan(1/3) —can you show why?). The peak error is therefore –5.7%, +5.4%.

Problem 2b—Is there a similar formula that gives even better results?

Answer 2b—Yes. One more multiplication operation gives a result that has less than 4% error:

Magnitude = 0.960433 × max(|x|, |y|) + 0.397826 × min(|x|, |y|)

This function is most negative at 0° and 45°, and most positive at 22.5°. The error is ± 3.96%. This form is well-suited to DSPs that have multiply-accumulate units. The two constants can be expressed as 62943/65536 and 26072/65536, respectively.

Contributor: David Tweed

Issue 262: EQ Answers

Problem 1—The classic two-transistor astable multivibrator is shown below. Typically, R2 and R3 have at least 10 times the value of R1 and R4. This circuit oscillates, with Q1 and Q2 turning on alternately. From the point in time in a cycle where Q1 first switches on, describe what happens until Q2 switches on.

Source: D. Tweed, CC262

Answer 1—Right before the moment Q1 switches on, C1 is charged to VCC – VBE, with its left end positive, and the left end of C2 has just reached +VBE. The right end of C2 is being held at VCE(SAT) by Q2.

Source: D. Tweed, CC262

So, as Q1 begins to switch on, it pulls the left end of C1 low, and this also pulls the right end of C1 low, cutting off Q2. This in turn allows the right end of C2 to rise, emphasizing the turn-on of Q1 by increasing the voltage (and current) at the base of Q1.

Once Q1 is fully on, the right end of C1 is now at VCE(SAT)– (VCC – VBE) (a fairly substantial negative voltage), and C1 now begins to charge in the other direction, through R2. Once the right end of C1 reaches +VBE, Q2 begins to turn on, starting the second half of the cycle.

Problem 2—What determines the time of one half-cycle of the oscillation? Does this depend on VCC?

Answer 2—The time of the half-cycle described previously is the time that it takes the right end of C1 to charge from –(VCC – (VBE + VCE(SAT))) to +VBE.

Now, keep in mind that the capacitor is charging “toward” +VCC, but it gets halted by the B-E junction of Q2 at +VBE. This charging is occuring at a rate determined by the time constant C1 × R2, and we’re basically interested in the time that it takes to move halfway from its starting value to its final value. This works out to –ln(0.5), or 0.693 times the R-C time constant.

As long as VCC >> VBE, the time does not depend on VCC. That isn’t to say, however, that VCC can be arbitrarily large. If it exceeds the reverse-breakdown voltage of the transistors’ B-E junctions, current will flow and perturb the timing.

Problem 3—Recently, a different circuit appeared on the web, shown below. Again, R2 and R3 are significantly larger than R1 and R4. The initial reaction of one observer was that this circuit can’t work, because there’s no DC bias path for either transistor. Is this assessment correct?

Source: D. Tweed, CC262

Answer 3—No, it isn’t. This circuit can oscillate just fine. Again, look at how C1 charges and discharges.

Source: D. Tweed, CC262

If C1 starts out discharged, it will charge through R1 and the B-E junction of Q2. This current will turn on Q2, holding its collector at ground (really VCE(SAT)) and preventing Q1 from turning on.

However, as C1 reaches full charge, the current through it decays below a level that will keep Q2 turned on. When it starts to turn off, its collector voltage rises, which also forces current into Q1′s base through C2. As Q1 begins to turn on, it pulls its collector low, which also pulls the base of Q2 lower, emphasizing its turn-off. The circuit quickly “snaps” to the other state, with Q1 on and Q2 off. C1 is discharged through Q1 and D2 at the same time that C2 begins charging through R4 and Q1′s B-E junction.

Problem 4—What role do R2 and R3 play in this circuit?

Answer 4—R2 and R3 never have more than ±VBE across them; as a result, the current through them is negligible relative to the current through the capacitors. In other words, they’re superfluous.

Question 5—Does the timing of this circuit depend on VCC? If not, what does it depend on?

Answer 5—The time from when one of the transistors turns on to when it turns off is determined by the currents flowing into its base and collector. When the current into the base drops below the value needed to sustain the current into the collector, the transistor begins to turn off, and the circuit feedback then insures that this happens quickly.

Looking at Q2, and ignoring the transient associated with discharging C2 for now, the collector current is set by R4. The initial base current is set by R1, but this decays exponentially with a time constant of R1 × C1.

Therefore, the primary determinant of the half-cycle time period (in addition to the R-C time constant) is the current transfer ratio, or hFE of each transistor. When the base current drops to a value of 1/hFE of the collector current, the transistor begins to turn off.

Since both currents scale in the same way with VCC, it has no direct effect on the timing. There is only a secondary effect if the value of hFE changes with the value of the collector current.

Contributor:  David Tweed