Second Gen of Open Virtual Platforms APIs

Imperas recently released of the second generation of the Open Virtual Platforms (OVP) APIs for building virtual platforms, additional Fast Processor Models, new models for popular peripherals, and new Extendable Platform Kits (EPKs). Open Virtual Platforms is a website for the OVP APIs, for the OVP models and platforms, for the OVPsim simulator, and for community discussion of virtual platforms on the OVP Forum. Publicly available and not proprietary, the models and platforms are available under the Apache Open Source License.

What’s new:

  • Support in the OVP APIs for unlimited hierarchy in virtual platforms
  • Support in the OVP APIs for virtualized passing of packets between peripheral models
  • ARC EM6 model
  • SPARCv8 model (developed by Friedrich Alexander University)
  • CAN, Ethernet, and USB models
  • Altera Cyclone III Nios II Linux and Cyclone V HPS Cortex-A9MPx2 Linux EPKs
  • Freescale Kinetis Cortex-M4 MQX and Vybrid Cortex-A5 MQX EPKs
  • Xilinx MicroBlaze ML505 Linux

With the ARC, ARM, and SPARC Fast Processor Models, 150 CPU models are now available. The performance for these models under a typical load is hundreds of millions of instructions per second, with peak performance of billions of instructions per second. The library of fast processor models includes models of ARM processors from the ARMv4 through the ARMv8 architecture, a complete set of MIPS models, plus models of Altera Nios II, ARC, PowerPC, Renesas, SPARC, and Xilinx MicroBlaze cores. Models are available with both C (OVP) interface and a C++ (SystemC) interfaces.

EPKs are designed to help accelerate embedded software development, debug, and test. They are virtual platforms (simulation models), including processor models plus peripheral models necessary to boot an operating system (OS) or run bare metal applications. The platform and peripheral models included in the EPKs are open source so you can easily add new models to the platform as well as modify the existing peripheral models. The example OS and applications are also included.

OVP models work with both the OVPsim and the Imperas simulators, including the QuantumLeap parallel simulation accelerator. OVPsim is used for academic and other noncommercial users (over 1,000 university departments current subscribe to the OVP website), while the Imperas products are for commercial users. Imperas M*SDK includes the OVP model library, iGen for model development, support for heterogeneous, multiprocessor/multicore processors, a comprehensive Verification, Analysis, and Profiling (VAP) tool set, plus an advanced three-dimensional (temporal, spatial, and abstraction) debug solution, 3Debug, for heterogeneous multicore processor, peripheral, and embedded software debug. The VAP tool suite contains more than 50 tools supporting hardware-dependent software development, including OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis. The Imperas SlipStreamer patent-pending binary interception technology enables these analytical tools to operate without any modification or instrumentation of the software source code (i.e., the tools are completely nonintrusive).

Source: Imperas

Virtual Prototyping — The Future’s So Bright

Virtual prototyping has been making its appearance in the embedded software arena since the late 1990s, steadily gaining acceptance as a valuable software development target. It initially rode the wave of rapid advances in chip process technology, which enabled multiple programmable cores on a single chip. This triggered a domino effect in product capabilities, with deep convergence of multiple functions in the same device becoming possible (smartphones being the most idiomatic example). In the semiconductor business landscape, ASIC companies needed to grow into system-on-chip (SoC) companies. The force of growing software content, complexity in general and the specialized nature of the low-level SoC software specifically was amplified by increased time-to-market pressure. Traditional development practices (mostly post-silicon) and targets (physical boards, FPGAs, etc.) couldn’t answer the call for true pre-silicon software development. In its first decade, virtual prototyping has established itself as the key “shift left” enabler in SoC development.Synopsys Diagram2

During the past five years, virtual prototyping has silently enabled embedded software to get past key inflection points and challenges. In the mid-2000s, the introduction of multi-core architectures was a key hurdle for embedded software, requiring considerable refactoring of existing single-threaded/-core software stacks. Virtual prototyping’s debug and visibility advantages facilitated the transition. Around the same time, security hardware was introduced in leading mobile SoCs to provide the basis for a secure computing platform, enabling user services like mobile commerce. The complexity of the new security software and hostility of a physical target for development—a device is supposed to be hacking resistant—made a good case for virtual prototyping, which provided ample visibility into the complex secure/non-secure domain interactions and a less hostile development target.

More recently, we observed adoption to address the SoC power consumption challenge. Power efficiency correlates directly with longer battery times, and dedicated chip hardware, both on- and off-chip, was introduced to manage power. The hardware flexibility offered is large, with final control left to the software. Complex power management software layers were introduced in high-level software stacks, and as virtual prototyping uniquely allows for an accurate representation of the complex hardware clocking and voltage schemes (other technologies like FPGAs can’t easily tackle this), it not only became an enabler for this new development, but also proved its value in software optimization for power and energy.

Today virtual prototyping is powering the architecture transition from 32- to 64-bit in the embedded space, through its use for early instruction-set market introduction, by enabling the porting of large existing stacks prior to the first 64-bit physical implementation and by helping the SoC companies transition their software.

The above inflection points appear in different markets earlier than others, with mobile being on the leading edge of embedded software advances, typically followed by networking and automotive. For instance, automotive is only now facing the multi-core challenge. As such, virtual prototyping repeatedly will play a key role in tackling a specific inflection point.

Looking towards the future, the technology will make further advances on two major fronts: contribution to software quality testing and deeper anchoring into other parts of the SoC design flow, through integration with technologies like hardware emulation and FPGA-based prototyping. With its value for the development phase of software accepted, tackling the next phase, software testing, is natural. The software nature of virtual prototypes allows for large parallel deployment, ideal for regression testing. Moreover, with continuous integration now accepted as a regular practice in desktop and web software development, we expect the embedded market to follow this trend. And with a virtual target making continuous integration straightforward, we expect virtual prototypes to play an important role in the trend’s adoption. Markets including automotive (and mil/aero) have stringent safety and reliability requirements, and virtual prototypes’ unique fault injection capability is starting to show its value. Security testing and analysis is still an unexplored area, which not only has potential for the Internet of Things market, but can have a broad impact as security is becoming commonplace for any connected system.

Having simulation performance track the increasing SoC design scale and keeping the modeling effort under tabs to deliver value sufficiently early are not small engineering challenges. Just-In-Time compilation gave a major boost in the 2003–2004 timeframe, but the number of SoC subsystems requires another turbocharge right now. Exploiting the subsystem-level parallelism through new technologies that map subsystem simulations to different cores in the host machine, and deep-insight performance profiling tools that allow performance tuning, will carry the technology forward for another 5-10 years. Raising the modeling abstraction level, increasing automation and promotion of subsystem-based re-use and assembly methodology are effective arms to tackle the modeling effort challenge.

With its challenges being dealt with, virtual prototypes will continue to drive a further shift left and to converge with the numerous inflection point challenges of embedded software ahead. In 5-10 years, this embedded virtualization technology will likely be as accepted as virtualization technology is in the IT space today. A bright future indeed!

Filip Thoen is the principal engineer for virtual prototyping products at Synopsys, the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. Thoen is responsible for the technical direction and architecture of the virtual prototyping products. Previously, he co-founded Virtio, a virtual prototyping leader later acquired by Synopsys, and served as its CTO. He has more than 15 years of experience in system simulation and embedded software, and has authored several articles, books, and patents in these areas. He holds MS and PhD degrees in Electrical Engineering from Catholic University of Leuven (Belgium).

This essay appears in Circuit Cellar 299 (June 2015).

High-Speed Laser Range Finder Board with IMU


The NavRanger-OEM

The NavRanger-OEM combines a 20,000 samples per second laser range finder with a nine-axis inertial measurement unit (IMU) on a single 3“ × 6“ (7.7 × 15.3 cm) circuit board. The board features I/O resources and processing capability for application-specific control solutions.

The NavRanger‘s laser range finder measures the time of flight of a short light pulse from an IR laser. The time to digital converter has a 65-ps resolution (i.e., approximately 1 cm). The Class 1M laser has a 10-ns pulse width, a 0.8 mW average power, and a 9° × 25° divergence without optics. The detector comprises an avalanche photo diode with a two-point variable-gain amplifier and variable threshold digitizer. These features enable a 10-cm × 10-cm piece of white paper to be detected at 30 m with a laser collimator and 25-mm receiver optics.

The range finder includes I/O to build a robot or scan a solution. The wide range 9-to-28-V input supply voltage enables operation in 12- and 24-V battery environments. The NavRanger‘s IMU is an InvenSense nine-axis MPU-9150, which combines an accelerometer, a gyroscope, and a magnetometer on one chip. A 32-bit Freescale ColdFire MCF52255 microcontroller provides the processing the power and additional I/O. USB and CAN buses provide the board’s high-speed interfaces. The board also has connectors and power to mount a Digi International XBee wireless module and a TTL GPS.

The board comes with embedded software and a client application that runs on a Windows PC or Mac OS X. It also includes modifiable source code for the embedded and client applications. The NavRanger-OEM costs $495.

Integrated Knowledge Systems, Inc.