Op-Amp Versus Comparator (EE Tip #128)

Practically every lecture course or textbook on electronics describes how to use an operational amplifier as a comparator. Here we look at the possibility in more detail, and see how it can often be a very poor idea.

The idea behind the comparator configuration is simple. An op-amp has a very high open-loop DC gain which means that even a tiny differential input voltage will drive the output to one extreme or the other. If the voltage at the non-inverting (“+”) input is greater than that at the inverting (“–“) input the output goes high; otherwise the output goes low. In other words the two voltages are compared and the output is a binary indication of which of the two is the greater.

Figure 1: SPICE simulation results: an LT1028 op-amp pressed into service as a comparator versus a real comparator type LT1720.

Figure 1: SPICE simulation results: an LT1028 op-amp pressed into service as a comparator versus a real comparator type LT1720.

So the op-amp looks like the perfect device to use as a comparator. But why then do there exist special-purpose comparator devices? Looked at from the outside, op-amps and comparators appear indistinguishable. Besides power connections, they both have “+” and “–” inputs and a single output. Taking a look at the internal circuit diagram, again the two devices appear broadly very similar (although a comparator device with an open-collector or open-drain output does look more obviously different from an op-amp). The big difference, which is not apparent without looking at the circuit more closely, is that the output stages of operational amplifiers are designed for linear operation, with the general aim of amplifying the input signal with as little distortion as possible (assuming that some negative feedback is provided), but in the case of a comparator the output circuit is designed to operate in saturation, that is, to switch between the upper and lower output voltage limits without the provision of external feedback. Comparators often also offer a ground connection in addition to the usual power connections, and provide digital logic levels at their outputs while accepting symmetrical analogue input signals.

What do these differences mean in practice? Comparators can react very quickly to changes in their input voltages with short propagation delays and output rise- and fall-times all specified by the manufacturer.

In contrast, because op-amps are not expected to be used in this mode, manufacturers tend not to give explicit specifications for propagation delay and rise- and fall-times (although they do normally specify slew rate), and these characteristics can be considerably poorer for op-amps than for comparators. To take an extreme example, a low-power op-amp might have a propagation delay measured in milliseconds, whereas a comparator might react in nanoseconds: a million times faster.

There is a further problem with op-amps. Many devices exhibit significantly increased power consumption when the output is in saturation, the resulting power dissipation on occasion being enough to destroy the device. Also, many op-amps (those not advertised as having “rail-to-rail outputs”) are not capable of driving their outputs close to the supply rails, for example having a maximum output voltage of 3 V with a 5-V supply. There can also be restrictions on the inputs. Some op-amps are equipped with antiparallel diodes across their input terminals, which prevent differential input voltages of more than about 0.6 V, whereas comparators’ inputs are often allowed to vary over the whole supply range.

Of course, there are many noncritical applications where an op-amp will work perfectly acceptably as a comparator, but it is not a practice to be recommended. The skeptic should lash up a quick test with a comparator and an op-amp side-by-side, each fed with a squarewave signal with rapid edges. Some of the potential pitfalls are shown up more easily in simulation, such as the possibility of an op-amp being so slow that it entirely misses a narrow pulse. It is hard to guarantee circuit performance, current consumption, and even the survival of the device.

The illustrations show a SPICE simulation of a relatively nimble op-amp (an LT1028 with a minimum slew rate of 11 V/µs) and a type LT1720 comparator. It is clear that the comparator responds sooner and with a much shorter rise-time. Its output swings all the way to +5 V rather than the 3 V managed by the op-amp. The situation is similar when the output swings low: the op-amp is much slower and only reaches an output voltage of –3 V rather than –5 V. The original squarewave is hardly recognizable at the op-amp’s output. Although the LT1028 cannot achieve its maximum specified gain with a –5-V supply, it is still a factor of at least 20 faster than an LM324 (with a slew rate of 0.5 V/µs); what the latter would make of our squarewave would not be a pretty sight. The op-amp fails to cope at all with shorter pulses, which are then effectively “swallowed,” while the comparator continues to handle them without difficulty.

Worthwhile further reading on this subject is Texas Instruments application note SLOA067 by Bruce Carter entitled “Op Amps and Comparators—Don’t Confuse Them!.”— Michael Holzl, Elektor January 2011

CircuitCellar.com is an Elektor International Media publication.

Build an Adequate Test Bench (EE Tip #127)

It’s in our makeup as engineers that we want to test our newly received boards as soon as possible. We just can’t wait to connect them to a power supply and then use our test bench equipment (e.g., generators, oscilloscopes, switches or LEDs, and so on) for simulation.

Circuit Cellar columnist Robert Lacoste's workspace in Chaville, France.

Circuit Cellar columnist Robert Lacoste’s clean, orderly workspace in Chaville, France.

But due to our haste, the result is usually a PCB under test lying on a crowded workbench in the middle of a mesh of test cables, alligator clamps, prototyping boards, and other probes. Experience shows that the probability of a short circuit or mismatched connection is high during this phase of engineering excitement.

Test Board

Rather than requiring a mesh of test wires, it is often wise to develop a small test PCB that will drastically simplify the test phase. Here the ancillary board provided a clean way to connect a Microchip Technology ICD3 debugger, a JTAG emulator, a debug analyzer, and a power supply input.

Take your time: prepare a real test bench to which you can connect your board. It could be as simple as a clean desk with properly labeled wires, but you might also need to anticipate the design of a test PCB in order to simplify the cabling.—Robert Lacoste, “Mixed-Signal Designs,” CC25:25th Anniversary Issue, 2013. 

 

A Wire Is an Inductor (EE Tip #126)

I’m confident you know that you should keep wires and PCB tracks as short as possible. But I’m also sure that you will underestimate this problem fairly frequently.

Remember that 1 cm of a 0.25-mm-wide PCB track is roughly equivalent to an inductance of 10 nH. If this 10 nH is paired with, say, a 10-pF capacitor, that gives a resonant frequency as low as 500 MHz, which is easily below the third or fifth harmonics of the clock frequencies commonly seen on modern high-speed digital boards. Similarly, a 1-cm-long track will jeopardize the performances of any RF system such as a 2.4-GHz transceiver. There is only one solution: keep tracks and wires as short as possible. If you can’t, then use impedance-matched tracks.

Remember this rule especially for the ground connections: any grounded pad of any part working in high frequencies should be directly connected by avia to the underlying ground plane. And this via must be as close as possible to the pad, not some millimeters away.

Just yesterday I did a design review of a customer’s RF PCB. A small 0402 inductance was grounded through a via that was 3 mm away. It was a bad idea because the inductance was as low as 1 nH. Those 3 mm changed its value completely.—Robert Lacoste, “Mixed-Signal Designs,” CC25:25th Anniversary Issue, 2013. 

Wireless Product Regulations (EE Tip #123)

Are you working on a wireless design that you’d like to bring to market? If so, be sure to anticipate regulatory constraints right from the start. Planning upfront will save you a lot of time, money, and hassle.

Electrical engineer Robert Lacoste notes:

Unless you’re working on a prototype that won’t ever leave your lab, there is a high probability that you will need to comply with some regulations. FCC and CE are the most common, but you’ll also find local regulations as well as product-class requirements for a broad range of products, from toys to safety devices to motor-based machines. (Refer to my article “CE Marking in a Nutshell,” Circuit Cellar 257, for more information.CE Mark

Let’s say you design a wireless gizmo for the U.S. market and later find that your customers want to use it in Europe. This means you lose years of work, as well as profits, because you overlooked your customers’ needs and the regulations in place in different locales.

When designing a wireless gizmo that will be used outside the U.S., having adequate information from the start will help you make good decisions. An example would be selecting a worldwide-enabled band like the ubiquitous 2.4 GHz. Similarly, don’t forget that EMC/ESD regulations require that nearly all inputs and outputs should be protected against surge transients. If you forget this, your beautiful, expensive prototype may not survive its first day at the test lab.

Lacoste’s full article appeared in Circuit Cellar’s anniversary issue, CC25.

DDS Basics (EE Tip #122)

The simplest form of a digital waveform synthesizer is a table look-up generator (see Figure 1). Just program a period of the desired waveform in a digital memory (Why not an EPROM for old timers?), connect a binary counter to the address lines of the memory, connect a DAC to the memory data lines, keep the memory in Read mode, clock the counter with a fixed-frequency oscillator FCLOCK, and voilà, you’ve got a waveform on the DAC output. Don’t forget to add a low-pass filter to clean the output signal, with, as you know, a cut-off frequency a little less than FCLOCK/2 to please Mr. Nyquist.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

This design works, but it is not too flexible. If you want to change the output frequency, you need to change the clock frequency, which is not easy to do, especially if you need a fine resolution.

The direct digital synthesizer (DDS) architecture is an improvement on this original design (see Figure 2). Rather than add one to the table look-up address counter at each clock pulse like the counter did in the previous example, a DDS uses an N-bit long-phase register and adds a fixed-phase increment (W) at each clock pulse to this register.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

N can be quite high (e.g., 32 or 48 bits), so only the most significant bits of the phase register are used to select a value from the phase-to-amplitude look-up table, which is usually nothing more than a ROM preprogrammed with a sine waveform. Assume that you are using the P most significant bits as an address. Then the output of the lookup table is routed to a DAC. And, of course, the analog signal finally goes through a low-pass filter, which is called a “reconstruction filter.” You will understand why in a minute.

How does it work? If the phase increment W is set to one, you will need 2N clock pulses to go through all of the values of the look-up table. One sine period will be generated on the FOUT output each 2N clock pulses, exactly like the aforementioned counter-based architecture. If W is 2, it will be twice as fast and the output frequency will be doubled. As you know, you need a little more than two samples per period to be able to reconstruct a sine signal, so the maximum value of W is 2N–1 – 1. The formula giving the output frequency based on the phase increment is then:DDS-EEtip-122-eq1

Don’t be confused. It is not a simple programmable divider because the phase register doesn’t loop back to the same value after each generated period. The table in Figure 3 may help you understand it.

Figure 3: his spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

Figure 3: This spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

What make a DDS a fantastic building block are the numeric examples. Just take a standard, low-performance DDS with a phase register of N = 32 bits and a reference clock FCLOCK = 20 MHz. Your DDS can then generate any frequency from DC to nearly 10 MHz with a resolution of the following:DDS-EEtip-122-eq2

Not bad. In fact, the maximum frequency will be a little lower due to constraints on the low-pass filter.—Robert Lacoste, “Direct Digital Synthesis 101,” Circuit Cellar 217, 2008. The issue is available in the CC Webshop.