DFT Plugin Added to Zuken Design Suite

Zuken  and XJTAG have entered into a partnership to enhance Zuken’s CR-8000 with a design for test (DFT) capability that will improve test coverage during schematic entry. The capability is based on XJTAG’s DFT Assistant, and will be available later this year as a free plugin for Zuken’s CR-8000 Design Gateway users. CR-8000 is a native 3D product-XJTAG-DFT-Assistant-768x435centric design platform for PCB-based systems. CR-8000 directly supports architecture design, concurrent multi-board PCB design, chip/package/board co-design and full 3D MCAD co-design. CR-8000 Design Gateway is Zuken’s platform for logical circuit design and verification.

Increasingly, PCBs are densely populated making it difficult to gain manufacturing test access to pins under many packages, such as ball grid arrays (BGAs). JTAG was designed to enable test access, so an optimized JTAG design can have a positive impact on ROI. Failure to optimize JTAG test coverage at an early design stage can increase manufacturing costs and possibly require a board re-design. XJTAG DFT Assistant will help to validate correct JTAG chain connectivity while displaying boundary scan access and coverage onto the schematic diagram through full integration with CR-8000 Design Gateway.

Zuken | www.us.zuken.com

New Version of Altium Designer Previewed

Altium has completed an exclusive preview tour of its Altium Designer 18 at a series of upcoming global PCB design conferences. Altium Designer continues its focus on delivering new, easy-to-use and productivity enhancing PCB design tools as part of a single, unified application. Leveraging feedback and suggestions from the design community, Altium Designer 18 features capability updates and performance optimizations to significantly enhance user experience and productivity. In addition to the easy-to-use, modernized user interface, Altium Designer 18 will also feature a much anticipated upgrade to 64-bit architecture and multi-threading for greater stability, speed, and functionality. These updates will allow designers to increase their design speed and task execution, and also provide more flexibility and control, simplifying the overall design process.

Fast and High-Quality RoutingThe Altium Designer 18 release significantly enhances user experience and productivity with a modern interface to simplify the design experience and enable unprecedented performance optimization, aided by 64-Bit architecture and multi-threading for greater stability, speed, and functionality during PCB design.

Connectivity management and enhanced 3D engine allows you to render design models and multi-board assemblies – faster and with better shading and realism. Real-time BOM management in Altium Design 18 links the latest supplier part information to the BOM, enabling users to make educated design decisions on their own timeline. A new, cohesive user interface provides a fresh and intuitive environment, and optimizations that enable unparalleled visualization of your design workflow. Fast and high-quality routing is provided by visual Constraints and user-guided automation. These enable you to route complex topologies across layers. In other words, it routes at the speed of a computer, but the quality of a human.

Altium | www.altium.com

Cadence Adds Real-Time DFM PCB Design

Cadence Design Systems provides Cadence Allegro PCB DesignTrue DFM technology that performs real-time, in-design design-for-manufacturing (DFM) checks integrated with electrical, physical and spacing design rule checks (DRCs). The technology, integrated into the Allegro PCB Editor, enables PCB designers to identify and correct errors immediately, long before manufacturing signoff. By finding errors earlier, design teams reduce rework, shorten design cycles and accelerate the new product development and introduction process, potentially saving at least one day per iteration and days to weeks overall.

Cadence originalUnlike manufacturing signoff tools that are run in batch mode when performing DFM checks, DesignTrue DFM technology provides continuous in-design feedback while designing, eliminating the frustrating and time-consuming design-verify-fix iterations between PCB designers and DFM checking teams. By the time PCB designers reach final DFM signoff, they already know their design meets manufacturing rules, resulting in a smoother signoff and handoff to the manufacturing partner and a shorter, more predictable design cycle.

Introduced in September, DesignTrue DFM technology is consistent with the proven Allegro constraint-driven design flow and online checking solution currently used for electrical, physical and spacing rules. DesignTrue DFM technology provides a wide set of checks to ensure design manufacturability. Spacing between copper features such as traces, pins, vias relative to the board outline and other copper features can be verified in real time, independent of electrical and net-based rules.

The new technology makes it easy to configure, apply contextually and reuse manufacturing rules. DesignTrue DFM technology supports the import and export of DFM rules and addresses more than 2,000 advanced checks. In addition, it employs a new and more user-friendly DRC browser capable of addressing one class of errors at a time. Constraints are highly configurable with the ability to enable and disable groups and whole categories of rules, or individual rules. Rules can be applied in etch mode, non-etch mode, and in stack-up mode, giving designers the ability to isolate layers, geometries and cutouts. The new browser also features an integrated DRC description with graphics, characterizes DRCs by type and provides a DRC count chart. Users can quickly sort, browse and review, as well as waive and unwaive DRCs.

Cadence Design Systems | www.cadence.com