LF Resonator Filter

Frequency Measurements

In Ed’s November article he described how an Arduino-based tester automatically measures a resonator’s frequency response to produce data defining its electrical parameters. Here, he examines the results of those measurements and delves into variable series capacitance as measurement aid.

By Ed Nisley

Quartz resonators—also known as “crystals”—normally set the frequency of a clock oscillator circuit to a precise value, but they can also become filters passing analog signals. Because resonators have an extremely high Q, the filters have a very narrow bandwidth and require precise center-frequency tuning. The Arduino-based tester I described in my November 2017 article (Circuit Cellar 328) automatically measures a resonator’s frequency response to produce the data defining its electrical parameters for use as either an ordinary oscillator or a filter isolating the 60 kHz WWVB signal from the surrounding RF clutter.

In this article, I’ll describe the results of those measurements, explain a tester modification to measure the resonator’s response with a variable series capacitance, then show what a resonator filter does to the 60 kHz WWVB preamplifier’s response.

Resonator Frequencies

Over the course of a few months, I bought two lots of 25 quartz tuning fork resonators from eBay, measured all 50 resonators, then converted the data into the histograms in Figure 1. The blue bars show the series resonant frequencies form a reasonably smooth distribution around 59996.1 Hz, 4 Hz below the nominal 60 kHz. A 24 pF series capacitance shifted the resonances upward by 1.7 Hz to produce a similar distribution of the red bars around 59997.8 Hz, showing the resonators behave as expected.

FIGURE 1
The blue bars summarize the series
resonant frequencies of fifty tuning
fork resonators. Inserting a 24-pF
series capacitor shifts the resonant
frequencies upward by about 1.7 Hz.

In contrast, refer to the magnetic sensitivity histograms of the Hall effect sensors in my May 2015 article (Circuit Cellar 298). Those eBay parts apparently came from production-line reject bins, because I got only the parts with responses far from their nominal value. My experience suggests you should not expect cheap electronic parts bought from eBay to meet their specifications and you must measure what you get.

The resonator responses cluster below 60.000 kHz, because they’re intended to be built into oscillator circuits with specific values of external capacitances to set the final frequency. For example, most digital oscillators use a Pierce topology with the resonator connected as a feedback element for a CMOS inverter biased into its linear range and a capacitor from each resonator lead to ground. Those oscillators operate near the resonator’s parallel resonance frequency, with the final frequency pulled slightly higher by the load capacitors. …

Read the full article in the January 330 issue of Circuit Cellar

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Numeric Precision vs. DDS Calculations

Using the full frequency resolution of a direct digital synthesizer chip outstrips the capabilities of floating point numbers. Ed takes a look at what’s needed for high-resolution frequency calibration and measurements.

By Ed Nisley

As you saw in my July article, the filter bandwidths and frequency resolution required to characterize low-frequency quartz resonators far exceeded the capabilities of my bench instruments. I decided to take a look at building a special-purpose resonator tester around a cheap direct digital synthesizer sine-wave source, because DDS generators have

PHOTO 1 A knockoff Arduino Nano controls a generic AD9850 direct digital synthesizer circuit, both plugged into standard 0.1 inch headers, with hand-wiring connections below the proto board. The SMA connector provides a mechanically rugged output from the board; the DDS frequencies don’t require its RF properties.

PHOTO 1
A knockoff Arduino Nano controls a generic AD9850 direct digital synthesizer circuit, both plugged into standard 0.1 inch headers, with hand-wiring connections below the proto board. The SMA connector provides a mechanically rugged output from the board; the DDS frequencies don’t require its RF properties.

advantages over traditional analog oscillators and frequency counters in computer-controlled measurement systems.

Of course, nothing is ever so simple as it seems. In this article, I’ll explain how numeric precision affects Direct Digital Synthesis (DDS) output frequency calculations, work through the effects of floating-point and fixed-point arithmetic, and show how a carefully tweaked DDS oscillator frequency varies with temperature.

DDS Calculations

You can think of a direct digital synthesizer as a lookup table holding the digitized values of an analog waveform, a counter addressing the table entries in ascending order, and a DAC converting the numbers to analog voltages. The Analog Devices AD8950 DDS chip in Photo 1 has the equivalent of a table with 232 10-bit entries defining a sine wave, a counter clocked at 125 MHz, and a differential output current-mode DAC. The PCB, complete with the DDS and a 125 MHz quartz oscillator, costs under $20 on eBay or Amazon. …

Read the full article in the September 326 issue of Circuit Cellar

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DDS Basics (EE Tip #122)

The simplest form of a digital waveform synthesizer is a table look-up generator (see Figure 1). Just program a period of the desired waveform in a digital memory (Why not an EPROM for old timers?), connect a binary counter to the address lines of the memory, connect a DAC to the memory data lines, keep the memory in Read mode, clock the counter with a fixed-frequency oscillator FCLOCK, and voilà, you’ve got a waveform on the DAC output. Don’t forget to add a low-pass filter to clean the output signal, with, as you know, a cut-off frequency a little less than FCLOCK/2 to please Mr. Nyquist.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

This design works, but it is not too flexible. If you want to change the output frequency, you need to change the clock frequency, which is not easy to do, especially if you need a fine resolution.

The direct digital synthesizer (DDS) architecture is an improvement on this original design (see Figure 2). Rather than add one to the table look-up address counter at each clock pulse like the counter did in the previous example, a DDS uses an N-bit long-phase register and adds a fixed-phase increment (W) at each clock pulse to this register.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

N can be quite high (e.g., 32 or 48 bits), so only the most significant bits of the phase register are used to select a value from the phase-to-amplitude look-up table, which is usually nothing more than a ROM preprogrammed with a sine waveform. Assume that you are using the P most significant bits as an address. Then the output of the lookup table is routed to a DAC. And, of course, the analog signal finally goes through a low-pass filter, which is called a “reconstruction filter.” You will understand why in a minute.

How does it work? If the phase increment W is set to one, you will need 2N clock pulses to go through all of the values of the look-up table. One sine period will be generated on the FOUT output each 2N clock pulses, exactly like the aforementioned counter-based architecture. If W is 2, it will be twice as fast and the output frequency will be doubled. As you know, you need a little more than two samples per period to be able to reconstruct a sine signal, so the maximum value of W is 2N–1 – 1. The formula giving the output frequency based on the phase increment is then:DDS-EEtip-122-eq1

Don’t be confused. It is not a simple programmable divider because the phase register doesn’t loop back to the same value after each generated period. The table in Figure 3 may help you understand it.

Figure 3: his spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

Figure 3: This spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

What make a DDS a fantastic building block are the numeric examples. Just take a standard, low-performance DDS with a phase register of N = 32 bits and a reference clock FCLOCK = 20 MHz. Your DDS can then generate any frequency from DC to nearly 10 MHz with a resolution of the following:DDS-EEtip-122-eq2

Not bad. In fact, the maximum frequency will be a little lower due to constraints on the low-pass filter.—Robert Lacoste, “Direct Digital Synthesis 101,” Circuit Cellar 217, 2008. The issue is available in the CC Webshop.