Wearables Drive Demand for Extreme Low Power Solutions

Wearables-Issue-329Wearable devices put extreme demands on the embedded electronics that make them work. Devices spanning across the consumer, fitness and medical markets all need a mix of low-power, low-cost and high-speed processing.



MCUs & Analog ICs Meet Needs

By Jeff Child, Editor-in-Chief

Designers of new wearable, connected devices are struggling to extend battery life for next-generation products, while at the same time increasing functionality and performance in smaller form factors. These devices include a variety of products such as smartwatches, physical activity monitors, heart rate monitors, smart headphones and more. The microcontrollers embedded in these devices must blend extreme low power with high integration. Meanwhile, analog and power solutions for wearables must likewise be highly integrated while serving up low quiescent currents.

Modern wearable electronic devices all share some common requirements. They have an extremely low budget for power consumption,. They tend not to be suited for replaceable batteries and therefore must be rechargeable. They also usually require some kind of wireless connectivity. To meet those needs chip vendors—primarily from the microcontroller and analog markets—keep advancing solutions that consume extremely low levels of power and manage that power. This technology vendors are tasked to keep up with a wearable device market that IDC forecasts will experience a compound annual growth rate (CAGR) of 18.4% in 2020.

MCU and BLE Combo

Following all those trends at once is Cypress Semiconductor’s PSoC 6 BLE. In September the company made its public release of the PSoC 6 BLE Pioneer Kit and PSoC Creator Integrated Design Environment (IDE) software version 4.2 that enable designers to begin developing with the PSoC 6. The PSoC 6 BLE is has built-in Bluetooth Low Energy (BLE) wireless connectivity and integrated hardware-based security.

According to Cypress, the company had more than 2,500 embedded engineer customers registering for the PSoC 6 BLE early adopter program in just a few months. Early adopters are using the flexible dual-core architecture of PSoC 6, using the ARM Cortex-M4 core as a host processor and the Cortex-M0+ core to manage peripheral functions such as capacitive sensing, BLE connectivity and sensor aggregation. Early adopter applications include wearables, personal medical devices, wireless speakers and more. Designers are also using the built-in security features in PSoC 6 to help guard against unwanted access to data.

The PSoC BLE Pioneer Kit features a PSoC 63 MCU with BLE connectivity (Photo 1). The kit enables development of modern touch and gesture-based interfaces that are robust and reliable with a linear slider, touch buttons and proximity sensors based on the latest generation of Cypress’ CapSense capacitive-sensing technology. Designers can also use the board to add USB Power Delivery (PD) with its Cypress EZ-PD CCG3 USB-C controller. The development kit also includes a 2.7-inch E-ink Display Shield add-on board (CY8CKIT-028-EPD) with thermistor, digital mic and 9-axes motion sensor.

Photo 1 The PSoC BLE Pioneer Kit features a PSoC 63 MCU with BLE connectivity. The kit enables development of modern touch and gesture-based interfaces that are robust and reliable with a linear slider, touch buttons and proximity sensors based using Cypress’ CapSense capacitive-sensing technology.

Photo 1
The PSoC BLE Pioneer Kit features a PSoC 63 MCU with BLE connectivity. The kit enables development of modern touch and gesture-based interfaces that are robust and reliable with a linear slider, touch buttons and proximity sensors based using Cypress’ CapSense capacitive-sensing technology.

Deep Sleep Current Levels

Extreme low power was also the theme behind Microchip Technology’s PIC32MX1/2 XLP family that the company announced in June. The 33-bit PIC32MX1/2 XLP offers current PIC32MX system developers an easy migration path to achieve higher performance at much lower power. It enables both increased functions and longer battery life in portable applications. According to Microchip, the new MCU family increases performance in small pin-count devices with little code rework for existing customers.

Microchip’s XLP technology is designed for wearable technology, wireless sensor networks and other smart connected devices and offers low current operating modes for Run and Sleep, where extreme low-power applications spend 90% to 99% of their time. XLP technology will enable Sleep and Deep Sleep shutdown states on the PIC32MX1/2 XLP devices, enabling Deep Sleep currents down to 673 nA. The devices offer over 40% more performance than the existing PIC32MX1/2 portfolio while reducing average currents by 50%. Figure 1 shows an XLP MCU used in a health/fitness wearable application.


Figure 1 Shown here is a Microchip XLP MCU used in a health and fitness wearable application.

The PIC32MX1/2 XLP family is available in a range of memory configurations with 128/256 kB flash and 32/64 kB of RAM in packages ranging from 28- to 44-pins. They also include a diverse set of peripherals at a low cost including I2S for digital audio, 116 DMIPS performance for executing audio and advanced control applications, a 10-bit, 1 Msps, 13-channel ADC and serial communications peripherals. The PIC32MX2 series also supports USB-device, host and OTG functionality.

In addition to the hardware peripheral features, the series is supported by Microchip’s MPLAB Harmony Software Development Framework, which simplifies development cycles by integrating the license, resale and support of Microchip and third-party middleware, drivers, libraries and RTOSes. Specifically, Microchip’s readily available software packages such as Bluetooth audio development suites, audio equalizer filter libraries, decoders (including AAC, MP3, SBC), sample rate conversion libraries and USB stacks will reduce the development time of wearable device applications.

Transactions with Wearables

Among the new features of some wearable devices is the ability to do contactless transactions. Today’s consumers have become quite comfortable with making secure transactions using their smart devices. As a result, traditional card manufacturers want to extend their offerings into contactless wearable products for uses such as payments, ticketing and access control. These can be difficult to implement within tight size and cost constraints, because conventional separate NFC-radio and security chips demand extra space and complicate design. In addition, wearable form factors tend to need small antennas that can restrict communication performance.

Supporting those capabilities in wearables, ST Microelectronics in October unveiled its technology for easy and secure contactless transactions using electronic wristbands or fashionwear like watches or jewelry. The ST53G System-in-Package solution combines the company’s expertise in Near Field Communication (NFC) and secure-transaction chips. ST’s new ST53G System-in-Package combines a miniaturized and enhanced NFC radio with a secure banking chip in one compact 4 mm x 4 mm module (Figure 2). The company’s proprietary boosted-NFC technology enables wearables with small antennas to deliver a great user experience when interacting with card readers over typical contactless distances.

Figure 2 ST’s ST53G System-in-Package combines a miniaturized and enhanced NFC radio with a secure banking chip in one compact 4 mm x 4 mm module.

Figure 2
ST’s ST53G System-in-Package combines a miniaturized and enhanced NFC radio with a secure banking chip in one compact 4 mm x 4 mm module.

The simplicity of this all-in-one module helps card enables embedded developers to quickly design functional and attractive wearables that can range from fashion items to one-time devices like event wristbands. ST offers an extensive development ecosystem, including radio-tuning tools and pre-defined antenna configurations. The ST53G meets all relevant card-industry standards, including EMVCo compliance, ISO/IEC-14443 NFC card emulation, and MIFARE ticketing specifications. The ST53G can host ready-to-use STPay smartcard operating systems and optional VISA/ Mastercard/JCB-certified banking applications pre-loaded on the secure microcontroller.

Embedded Security for Wearables

The secure banking chip contained in the ST53G System-in-Package leverages ST’s proven ST31G480 secure microcontroller that is based on the ARM SC000 SecurCore processor. It features a secure architecture with a NESCRYPT coprocessor for public-key cryptography and hardware accelerators for algorithms like AES and triple-DES. Extensive anti-tamper protection including an active shield, environmental monitoring, a unique serial number for each die and protection against numerous other attacks are also built-in. These features complement software-based security running on the SC000 core to ensure the strongest possible protection for users’ credentials.

The contactless IC is the STS3922 RF booster, which uses active-load modulation (ALM) to maximize transaction range and omnidirectional radio performance in card-emulation mode. This enables wearable devices to be easy to use—with equal or better device-to-reader positioning tolerance than conventional contactless smartcards—even though a smaller antenna is used. Using ST53G contributes to final device cost optimization because small antennas can be etched onto the PCB at almost zero additional cost. In some cases, a challenging metallic case can itself be used as part of the RF antenna.

Automatic power and gain control, configurable sensitivity, and configurable signal/reader-field phase difference ensure consistent communication over all ranges. These enhance smooth interoperability with different types of readers and terminals including various transportation ticketing systems. The STS3922 has a dedicated secure-MCU wake-up output. That feature enables the ST53G System-in-Package to maximize battery life by powering down when not in use.

Power Regulation for Wearables

Designing today’s wearable devices requires not just low power on the MCU side. They also require sophisticated analog IC solutions that help regulate power and extend battery life as much as possible. Along those lines, Maxim Integrated in March announced its the MAX17222 nanoPower boost regulator with what the company claims is the industry’s highest efficiency and lowest quiescent current (IQ) of only 300 nA (Figure 3). The 0.4V to 5.5V input, 1.8V to 5V output boost regulator with 500 mA input current limit reduces solution size by up to 50% compared to similar products and offers 95% peak efficiency to minimize heat dissipation.

Figure 3 The MAX17222 boost regulator offers a low quiescent current of 300 nA, 0.4V to 5.5V input, 1.8V to 5V output and 500 mA input current limit.

Figure 3
The MAX17222 boost regulator offers a low quiescent current of 300 nA, 0.4V to 5.5V input, 1.8V to 5V output and 500 mA input current limit.

Aside from very low quiescent current, the MAX17222 also minimizes heat dissipation and shutdown current. In True Shutdown mode, the minuscule current draw of 0.5 nA virtually stops battery drain to provide the longest battery life and eliminate the need for external disconnect switches. The MAX17222 is internally compensated and requires only a single configuration resistor and small output filter for a full power solution. For ease of use, the boost regulator comes in tiny, density-optimized 0.88 mm x 1.4 mm 6-bump WLP and 2 mm x 2 mm 6-pin standard µDFN packages. It operates over a -40°C to +85°C temperature range.

Health monitoring wearable devices have their own particular analog design challenges. Targeting such needs, Analog Devices offers a low power, next-generation biopotential analog front end (AFE) which enables smaller, lighter and less obtrusive cardiac monitoring devices with longer battery life. The AD8233 AFE is a fully integrated, single-lead electrocardiogram (ECG) front end designed in one compact, easy-to-use component. Typically, developers need to design ECG front ends from individual components, which can add incremental cost and design time.

Health Monitoring Solution

The highly integrated, out-of-the-box AD8233 AFE eliminates these unnecessary costs and extra time, helping developers get products to market more quickly. Additionally, the device’s 2.0 mm × 1.7 mm size enables the design of wearable health devices that are smaller, lighter and easier to wear. Bulky, heavy and obtrusive monitors can be unpleasant for patients to wear and may even interfere with their everyday lives. Longer battery life is another crucial attribute for cardiac monitors and is vital to ensure continuous monitoring that provides accurate data without the interruption of a recharge or battery replacement. The AD8233 AFE’s low microamp-range power consumption results in greatly extended battery life.

Along with its small size, the single-supply (1.7 V to 3.5 V) AD8233 features extremely low quiescent current of 50 μA (typical); lead on/off detection even while in shutdown mode (less than 1 μA); and 80-dB common-mode rejection ratio (DC to 60 Hz). Electrical noise, a critical specification for cardiac-monitoring devices, is below 10 μV from 0.5 to 40 Hz. The AD8233 also allows for highly flexible filter configurations which are essential to consistent, confident operation in an inherently harsh electrical environment under a range of use cases. These configuarations include a two-pole adjustable high-pass filter, a three-pole adjustable low-pass filter with adjustable gain and an RFI filter. For ease-of-use and flexibility, it also includes an integrated right leg drive (RLD) amplifier with shutdown plus an uncommitted op amp. Analog Devices also offers an evaluation board, reference design, web based filter design tool and Spice model to facilitate design-in and speed time to market.

The AD8233CB-EBZ evaluation board contains an AD8233 heart rate monitor (HRM) front end conveniently mounted with the necessary components for initial evaluation in fitness applications (Photo 2). Inputs, outputs, supplies and leads off detection terminals are routed to test pins to simplify connectivity. Switches and jumpers are available for setting the input bias voltage, shutdown (SDN), right leg drive shutdown (RLD SDN), fast restore (FR) and AC/DC leads off detection mode. The AD8233CB-EBZ evaluation board is a 4-layer board with components mounted on the primary side only. Rubber feet are available on the secondary side for mechanical stability. The layout diagrams are provided as a visual aid and reference design.

Photo 2 The AD8233CB-EBZ evaluation board contains an AD8233 heart rate monitor (HRM) front end conveniently mounted with the necessary components for initial evaluation in fitness applications.

Photo 2
The AD8233CB-EBZ evaluation board contains an AD8233 heart rate monitor (HRM) front end conveniently mounted with the necessary components for initial evaluation in fitness applications.

Wireless Connectivity

Seamless wireless connectivity has pretty much become a given for today’s wearable devices. With that in mind, Cypress Semiconductor in September announced a new combo solution that delivers ultra-low power Wi-Fi and Bluetooth connectivity to extend battery life for wearables and portable audio applications. The new Cypress CYW43012 solution prolongs battery life by leveraging 28 nm process technology to cut power consumption up to 70% in receive mode and up to 80% in sleep mode when compared to current solutions. The solution is IEEE 802.11a/b/g/n-compliant and 802.11ac-friendly, meaning it is interoperable with 802.11ac access points using standard modes. This enables it to offer higher throughput and better energy efficiency, along with the enhanced security and coverage of 802.11ac Wi-Fi networks.

The CYW43012 combo chip’s advanced coexistence engine enables optimal combined performance for dual-band 2.4- and 5-GHz Wi-Fi and dual-mode Bluetooth/BLE 5.0 applications simultaneously. The CYW43012 solution is supported in Cypress’ all-inclusive, turnkey, WICED Studio IoT development platform, which streamlines the integration of wireless technologies for developers. According to Cypress, battery life is a key differentiator for connected devices like wearables. Users demand a great connected experience for longer without having to recharge.

The Cypress WICED Studio IoT development platform features an integrated and interoperable wireless software development kit (SDK). The SDK includes broadly deployed and rigorously tested Wi-Fi and Bluetooth protocol stacks, as well as simplified application programming interfaces that free developers from needing to learn complex wireless technologies. In line with the IoT trend toward dual-mode connectivity, the SDK supports Cypress’ Wi-Fi and Bluetooth combination solutions and its Bluetooth and Bluetooth Low Energy devices. The SDK enables cloud connectivity in minutes with its libraries that integrate popular cloud services such as Amazon Web Services, IBM Bluemix, Alibaba Cloud and Microsoft Azure, along with services from private cloud partners. WICED also supports iCloud remote access for Wi-Fi-based accessories that support Apple HomeKit, which enables hub-independent platforms that connect directly to Siri voice control and the Apple Home app remotely.

Cypress’ WICED Studio connectivity suite actually is MCU-agnostic and provides support for a variety of third-party MCUs to address the needs of complex IoT applications. The platform also enables cost-efficient solutions for simple IoT applications by integrating MCU functionality into the connectivity device. Wi-Fi and Bluetooth protocol stacks can run transparently on a host MCU or in embedded mode, allowing for architectures with common firmware.

As consumers push for more capabilities in their wearable products, they won’t tolerate any reduction in battery life. Along the way, wireless connectivity and embedded security will have to be supported. These conflicting trends will continue to challenge MCU and analog IC vendors to come up with more integrated solutions at ever lower power consumption levels.

Analog Devices | www.analog.com
Cypress Semiconductor | www.cypress.com
Microchip | www.microchip.com
ST Microelectronics | www.st.com
Maxim Integrated | www.maximintegrated.com

September Circuit Cellar: A Sneak Preview

The September (326) issue of Circuit Cellar magazine serves up a meaty selection of useful technology resources along with inspiring, interesting embedded electronics design articles.

Not a Circuit Cellar subscriber?  Don’t be left out! Sign up today:


Here’s a sneak preview of September Circuit Cellar:


Getting Started with PSoC Microcontrollers (Part 3): Data Conversion, Capacitive Sensing and More
In Part 3, Nishant Mittal gets into some if the PSoC’s more complex features like Data Conversion.

Implementing a Time-Oriented Task Manager for 8-bit PIC Microcontrollers
Pedro Bertoleti shows readers how to build a time-oriented task manager using Microchip’s PIC 16F628A 8-bit microcontroller.


Microcontrollers Beef Up Security Features: Defense in a Connected World
Jeff Child explores the various flavors of embedded security features that microcontroller vendors are adding to their devices.

Resources for Embedded Security: Hardware, Software and Services
Circuit Cellar collects four pages worth of info about companies that provide embedded security products, tools and services.


Using Power Audio Amplifiers in Untypical Ways (Part 1): Best Building Blocks
Petre Petrov shows readers how to use PAAs as universal building blocks to create analog signal generators, analog power supplies, voltage splitters and more.

Data Acquisition Advances Focus on Interfacing
Jeff Child discusses the latest data acquisition solutions, with a look at how interface technologies have evolved.

Future of IoT Communications: Will Upgraded Cellular Networks Benefit IoT?
This guest essay by Andrew Girson, CEO of Barr Group, explores how IoT will fare in the 5G network era.


Block Diagram Reduction and Automatic Tuning
George Novacek steps through how to think in terms of block diagrams to help you reduce system complexity early on in a design.

Numeric Precision vs. DDS Calculations
Using the full frequency resolution of a DDS chip outstrips the capabilities of floating point numbers. Ed Nisley looks at high-res frequency calibration and measurements in the DDS realm.

Deadbolt the Uninvited: Locked Out of My Home
In this Part 2 of Jeff Bachiochi’s electronic lock story, he gets into some of the power and remote-control issues of his electronic deadbolt lock project.

Diagnosing Performance Variations in HPC
Ayse K. Coskun delves into how application performance variations can cause inefficiency
in high-performance computing (HPC) systems and how to diagnose these variations.

August Circuit Cellar: A Sneak Preview

The August (325) issue of Circuit Cellar magazine is jammed packed with useful technical information and inspiring, intriguing embedded electronics design stories.

Not a Circuit Cellar subscriber?  Don’t be left out! Sign up today:


Here’s a sneak preview of August Circuit Cellar:


Digital Guitar Amplifier/ Effects Processor—Part 2
Brian Millier details the digital guitar amplifier/effects unit he built using two Teensy Arduino modules.

A Range of Power Supplies for Hollow-State Guitar Amplifiers
Richard Honeycutt compares several different power supplies used for hollow-state guitar amplifiers.


Firmware Upgrade with the PIC32
Nick Sicalides delves into performing firmware upgrades using a bootloader on the Microchip PIC32

Getting Started with PSoC Microcontrollers (Part 2): Putting PSoC to Work
Nishant Mittal goes even deeper on the Cypress PSoC providing some useful design examples.

Moore’s Law and the Chip Industry’s Perfect Storm
In this Interview Q&A Krste Asanovic explains RISC-V and the open sourcing of processor architecture.


Power Analysis of a Software DES Encryption Routine
Columnist Colin O’Flynn examines how to break a software implementation of the DES security routine.

Reliability and Failure Prediction: A New Take
Craig Armenti and Dave Wiens discuss a better way to simulate PCB vibration and acceleration.

Preventing Unwanted Entry
Columnist Jeff Bachiochi takes us inside his exploration of electronic lock systems, getting down to the fine details.

Future of Embedded Security: Wi-Fi to the Danger Zone
This guest essay by Adam Cecchetti, CEO of Deja vu Security, explains how memory leaks in your embedded system could have life or death consequences.


Automatic Control (Part 4) The Implementation
George Novacek describes the PID temperature controller he built for a meat smoker.

Fully Differential Amplifiers
Robert Lacoste sings the praises of fully differential amplifiers and presents a few designs using them.

Build an Embedded Systems Consulting Company (Part 5) Axiom Wrap-Up
Bob Japenga shares more insights on running a successful embedded design firm built to last.

Cypress Announces First Two-port USB-C Controller with Thunderbolt 3 Support

Cypress Semiconductor announced availability of a new USB-C controller with Power Delivery (PD) optimized for Thunderbolt notebook and desktop PCs, as well as docking stations. The EZ-PD CCG5 controller is the industry’s first two-port USB-C controller that supports the Thunderbolt alternate mode with Intel’s Thunderbolt 3 (Alpine Ridge) controllers. This is a programmable, highly-integrated controller that allows designers to easily add Thunderbolt alternate mode and USB Power Delivery 3.0 to USB-C ports in the PC ecosystem.

The new EZ-PD CCG5 controller enhances the plug-and-play USB-C user experience, while providing Bill-of-Material (BOM) integration with features such as built-in protection against shorts and electrostatic discharge. The highly integrated controller increases the reliability of a system by integrating Flash memory that can store two firmware images for fail-safe boot. It offers the EZ-PD family’s trademark programmability to keep up with evolving industry standards.

“The world’s leading PC makers have been closely monitoring the maturity of USB-C controllers to bring all of the universal connectivity and fast charging benefits of the standard to their customers,” says Ajay Srikrishna, vice president of Cypress’ Wired Connectivity Business Unit. “Our new EZ-PD CCG5 controller is optimized to enable the broad scale proliferation of USB-C in desktop and notebook PCs, as well as docking stations, and has already earned multiple design wins with top tier PC OEMs.”

The one-chip EZ-PD CCG5 solution minimizes bill-of-material costs for two USB-C ports by integrating 20V regulators, sideband (SBU) muxes, USB high-speed (HS) muxes, high-voltage power FET gate drivers, VBUS-short protection for configuration channel (CC) and SBU pins, dedicated hardware to protect the system against overvoltage, undervoltage and overcurrent fault conditions, and system-level electrostatic discharge (ESD) protection.

The USB Type-C standard is gaining rapid support with top-tier electronics manufacturers by enabling slim industrial designs, easy-to-use connectors and cables, and the ability to transmit multiple protocols and deliver up to 100W of power. As the USB Type-C standard continues to evolve, compliance and interoperability pose an ongoing challenge, but Cypress’ programmable EZ-PD controllers enable firmware upgradeability to keep up with changes and overcome interoperability issues. The EZ-PD CCG5 controller integrates an ARM Cortex-M0 and 128KB Flash with read-while-write functionality for firmware upgradeability.

The two-port EZ-PD CCG5 controller is now sampling in a 96-BGA (6×6 mm) package, and the one-port version is sampling in a 40-QFN (6×6 mm) package. The controller will be in production in the third quarter of 2017.

New PSoC 4 L-Series

Cypress Semiconductor Corp. recently introduced the PSoC 4 L-Series, which is an integrated single-chip solution with a 32-bit ARM-Cortex-M0 core. It features 256-KB flash memory, 98 general-purpose I/Os, 33 programmable analog and digital blocks, a USB device controller, and a control area network (CAN) interface. The PSoC 4 L-Series is well-suited for industrial and consumer applications requiring reliable user interfaces.Cypress PSOC 4 L

The PSoC 4 L-Series delivers up to 13 programmable analog blocks including 4 high-performance opamps, four current-output digital-to-analog converters (IDACs), two low-power comparators, a 12-bit SAR ADC and dual CapSense blocks with up to 94 capacitive-sensing channels. The programmable analog blocks enable you to create on-chip, custom analog front ends.

The PSoC 4 L-Series delivers up to 20 programmable digital blocks including eight timer/counter/PWM blocks, four serial communication blocks, and eight Universal Digital Blocks (UDBs)—programmable digital blocks that each contain two programmable logic devices, a programmable data path, and status and control registers. UDBs can be configured as coprocessors to offload compute-intensive tasks from the ARM Cortex-M0 core. The blocks also enable you to implement custom digital peripherals, state machines, or glue logic. Traditional microcontrollers typically require additional ICs to implement this functionality. The scalable PSoC 4 architecture is complemented by the easy-to-use PSoC Creator IDE and PSoC Components—free embedded ICs represented by an icon in the IDE.

The PSoC 4 L-Series is currently sampling with production expected in the first quarter of 2016. Parts will be available in 48-pin TQFP, 64-pin TQFP, 68-pin QFN and 124-pin VFBGA packages.

Source: Cypress Semiconductor

Radiation-Hardened QDR-II+ SRAMs Achieve QML Class V Certification

Cypress Semiconductor Corp. recently announced its radiation-hardened (RadHard) 72-Mb Quad Data Rate II+ (QDR-II+) SRAMs and 4-Mb fast asynchronous SRAMs have achieved Qualified Manufacturers List Class V and Class Q requirements—the highest standards of quality and reliability for aerospace-grade ICs.CypressSRAM

The 72-Mbit QDR-II+ SRAMs deliver industry-leading throughput performance up to 36 Gbps by leveraging the ability to read and write data simultaneously. This throughput, combined with complete random access of data and free memory controllers for FPGAs, enables reconfigurable computing platforms that allow satellites to be reprogrammed while in space. The devices also feature the industry’s lowest latency and are ideal for radar and networking applications used in space

Both new SRAM families employ Cypress’s patented RadStop technology, which enables uncompromised functionality in the face of radiation up to 300 krads. The devices are manufactured in the Cypress’s fabrication facility in Bloomington, Minnesota, which is Microelectronics Trusted Category 1A accredited.

The radiation-hardened 4-Mbit devices deliver access times of 10 ns at 85°C and 12 ns at 125°C. They are also the first 90-nm, QML-V qualified devices of their kind and are ideal for a wide range of space and military applications.

Cypress’s RadStop technology combines manufacturing process hardening and proprietary design techniques. With RadStop technology, the SRAMs deliver single event latch-up immunity and single event functional interrupt immunity at temperatures as high as 125°C.

The Rad-Hard 72-Mb QDR-II+ SRAMs are available in a 165-column grid array (CGA) package. The devices come in the following four part numbers and configurations with equivalent Defense Supply Center Columbus (DSCC) part numbers:

  • CYRS1542AV18-250GCMB (x18 bus width, burst of 2); Class V part number: 5962F1120101VXA
  • CYRS1543AV18-250GCMB (x18 bus width, burst of 4); Class V part number: 5962F1120102VXA
  • CYRS1544AV18-250GCMB (x36 bus width, burst of 2); Class V part number: 5962F1120201VXA
  • CYRS1545AV18-250GCMB  (x36 bus width, burst of 4); Class V part number: 5962F1120202VXA

The CYRS1049DV33-12FZMB (5962F1123501VXA) 4-Mb fast asynchronous SRAMs are available in a 36-pin ceramic flat package.

Source: Cypress Semiconductor

Q&A: Chris Paiano (Problem Solving & Design)

Chris Paiano is an Elko, NV-based problem engineer. His father introduced him to programming at an early age, and Chris has continued to team with his father to write software and firmware for some of his hardware designs. Chris has written dozens of unique application notes for the Cypress Semiconductor Programmable-System-on-Chip (PSoC) chipset. He is currently using PSoC in an innovative household project and dreams of finishing his concept for environmentally friendly electric/hybrid vehicle wheeldrive retrofit kits.

Chris Paiano working with his “office assistants” (bearded dragons)

You can read the complete interview in Circuit Cellar 272 March 2013.

NAN PRICE: Tell us a little about your background.

CHRIS PAIANO: I went to school in Orlando, FL, all the way through college at the University of Central Florida, where I obtained my bachelor’s degree in Computer Engineering.

I started at a very young age. My father always had an electronics workbench and I spent time there when I could. When I was 2 years old, he brought me home an Apple ][ with some floppy disks and told me there were games to be played—if I could only figure out how to make them work.

The Apple ][ was not the most user-friendly or intuitive computer system, by any means. In order to accomplish my important goal of playing video games, I had to learn how to work with the computer’s clunky command-line interface (CLI). Once I figured out how to make all the games work, I wanted to fully automate them so I didn’t have to go through all the manual steps to play them every time (also, so my friends could start them up without me). So, I spent much time developing automatic start-up scripts, from the Applesoft HELLO program to MS-DOS configuration start-up menus, supporting whatever memory management method was required to play certain games, along with icon-driven pre-Windows menu systems that made these early systems usable by my friends, family, and clients.

This evolved into more elaborate scripting and programming to fill the gaps where the tools I needed did not exist, so I had to create them. My possibilities really opened up when I began developing firmware to complement my father’s hardware designs.

NAN: Tell us about your company, Christopher Paiano Engineering (CpE).

CHRIS: I design and program prototypes for various clients. I provide them with ideas at various development stages, which I turn into something that they can mass produce. I’ve just redesigned my website (www.cpeproto.com), by the way. It has a sleeker, simple interface and is easier to navigate now. No more Java menu with annoying sound effects!

NAN: Several of your projects are built around the Cypress Semiconductor programmable system-on-chip (PSoC). Is that your go-to chipset?

CHRIS: Yes, mainly because of how versatile and capable it is. It seems to be sufficient to take care of most any embedded task or set of tasks that come to mind.

For example, recently, the proprietor of a local game/tech/arcade business approached me to build a custom, inexpensive door chime. He wanted customers to hear random, recognizable portal sounds from popular video games whenever customers entered or exited his shop.

I started with an inexpensive motion sensor product from a local superstore. I added a Cypress CY8C27443 PSoC, as I have several lying around for general projects. I made a copy of my “Playing WAV Files with a PSoC” app note project to modify.

I added code to randomly cycle through available sound clips in the memory and I was able to provide 1.9805 s of audio at 8 kHz with the 16 KB of RAM available in this chip. The client was happy with this. He settled on two portal sounds (from The Legend of Zelda and Super Mario Brothers) and the chime has been in use for several months now. Customer feedback has been excellent. Everyone entering the place immediately recognizes the sounds and loves it!

NAN: You’ve written more than 30 application notes for the Cypress chipset, including PongSoC and the Video RTA. Can you explain the process?

CHRIS: Sometimes Cypress would post bounties for app notes that they’d like to see written on a certain topic or capability. Other times, I’d have an interesting personal project for which I decided to utilize a PSoC. I would then decide it might make a good app note, so I’d write it up and submit it. Either way, I’d usually develop the project side-by-side with my father. (We make an excellent hardware/software team.) I work out whatever firmware and PC/smartphone apps may be necessary, and he builds the PSoC circuit board with which to test. Then, I document it all, arrange it, and edit it into an app note (or, in some cases, an article).

Sometimes a project is just too complex to squeeze into a single PSoC’s resources and the simplest solution is to just add another PSoC. Communication between PSoCs can be quick and easy to implement, so distributing tasks and maintaining synchronization is not too difficult. This was the solution for the video real-time analyzer (RTA) app note where, realistically, there were only enough internal analog resources to provide three filters in each PSoC. With the Video RTA, one just adds as many PSoCs to the bus as is necessary to achieve the desired analyzer resolution.

The PongSoC was a fun one! Once I learned it was possible to combine some internal PSoC modules and algorithms to generate a stable composite video signal, I immediately decided I wanted to try and utilize this new capability to recreate a Pong-like embedded game-on-a-chip. I could already generate sound effects and read potentiometers for paddle inputs, I just needed to work it all out. I had a great time doing so, testing it with friends and playing with the variables to tweak the gameplay, and so forth.

Additionally, all 40 of my PSoC application notes are now available in some capacity on my updated website, as Cypress does not actively market the older PSoC families that many of my projects utilized in the past. I get enough e-mail requests for source code and documentation from this collection, so I have just gone ahead and taken the time to restore as many as I could find from my archives to the new website.

NAN: Your two-part article series “PSoC Design Techniques” describes how to build an eight-channel mixer and how DSP effects and a user interface can be added to it (Circuit Cellar 216–217, 2008). Describe the design and why you chose this design concept.

CHRIS: This was a great challenge. In a chip that traditionally would only allow for four full audio pathways in the provided analog resources (four PGA modules utilizing the normal I/O paths provided by PSoC Designer), we managed to figure out a way to utilize the remaining switched-capacitor blocks to act as signal mixers and gain stages with enough live reconfigurable resources to add potentiometers to control volume for each channel. Since there was still plenty of code space, I went ahead and added some DSP effects (reverb and pitch shift) along with a voice menu and flash-settings memory.

I really wanted to showcase what efficient design and algorithms could accomplish in a single piece of silicon, and I’m quite pleased with the way this project turned out. I still use the resulting device on my workbench and in my setups. It comes in handy sometimes. I have not updated it at all. I’ve been using it as is and it is still available for purchase on my website for anyone interested in experimenting with one.

NAN: Are you currently working on or planning any microprocessor-based projects?

CHRIS: Currently, I’m working on a PSoC solution for my broken dishwasher.

Chris Paiano is developing a PSoC solution for a broken dishwasher. In addition to the fix, he plans to make it smartphone-controllable.

The control module on this appliance has failed, so I am wiring it into a PSoC to make it work again as well as add some new capabilities (such as keeping a wash/rinse/door open log so it can tell when the dishes contained within it are clean or dirty, and adding a Bluetooth module so I can check the status and control/program the appliance from my smartphone).

This is the type of personal project I like to work on in my free time. It also might make a good app note or article in the future, as it involves an Android application and Bluetooth communication. It also increases my capabilities, if I have to figure out anything new. And that is always good.

I am almost ready to hook it up to the dishwasher, let it try running through the cycles, and hope I don’t flood my house in the process. Ah, the pure excitement of engineering!

The entire interview is available in Circuit Cellar 272 March 2013.

DIY Cap-Touch Amp for Mobile Audio

Why buy an amp for your iPod or MP3 player when you can build your own? With the proper parts and a proven plan of action, you can craft a custom personal audio amp to suit your needs. Plus, hitting the workbench with some chips and PCB is much more exciting than ordering an amp online.

In the April 2012 issue of Circuit Cellar, Coleton Denninger and Jeremy Lichtenfeld write about a capacitive-touch, gain-controlled amplifier while studying at Camosun College in Canada. The design features a Cypress Semiconductor CY8C29466-24PXI PSoC, a Microchip Technology mTouch microcontroller, and a Texas Instruments TPA1517.

Denninger and Lichtenfeld write:

Since every kid and his dog owns an iPod, an MP3 player, or some other type of personal audio device, it made sense to build a personal audio amplifier (see Photo 1). The tough choices were how we were going to make it stand out enough to attract kids who already own high-end electronics and how we were going to do it with a budget of around $40…

The capacitive-touch stage of the personal audio amp (Source: C. Denninger & J. Lichtenfeld)

Our first concern was how we were going to mix and amplify the low-power audio input signals from iPods, microphones, and electric guitars. We decided to have a couple of different inputs, and we wanted stereo and mono outputs. After doing some extensive research, we chose to use the Cypress Semiconductors CY8C29466-24PXI programmable system-on-chip (PSoC). This enabled us to digitally mix and vary the low-power amplification using the programmable gain amplifiers and switched capacitor blocks. It also came in a convenient 28-pin DIP package that followed our design guidelines. Not only was it perfect for our design, but the product and developer online support forums for all of Cypress’s products were very helpful.
Let’s face it: mechanical switches and pots are fast becoming obsolete in the world of consumer electronics (not to mention costly when compared to other alternatives). This is why we decided to use capacitive-touch sensing to control the low-power gain. Why turn a potentiometer or push a switch when your finger comes pre-equipped with conductive electrolytes? We accomplished this capacitive touch using Microchip Technology’s mTouch Sensing Solutions series of 8-bit microcontrollers. …


The audio mixer flowchart

Who doesn’t like a little bit of a light show? We used the same aforementioned PIC, but implemented it as a voltage unit meter. This meter averaged out our output signal level and indicated via LEDs the peaks in the music played. Essentially, while you listen to your favorite beats, the amplifier will beat with you! …
This amp needed to have a bit of kick when it came to the output. We’re not talking about eardrum-bursting power, but we wanted to have decent quality with enough power to fill an average-sized room with sound. We decided to go with a Class AB audio amplifier—the TPA1517 from Texas Instruments (TI) to be exact. The TPA1517 is a stereo audio-power amplifier that contains two identical amplifiers capable of delivering 6 W per channel of continuous average power into a 4-Ω load. This quality chip is easy to implement. And at only a couple of bucks, it’s an affordable choice!


The power amplification stage of the personal audio amp (Souce: C. Denninger & J. Lichtenfeld)

The complete article—with a schematic, diagrams, and code—will appear in Circuit Cellar 261 (April 2012).