High-Speed CMOS DDR SDRAMs

AllianceMemoryThe AS4C4M16D1-5TIN, the AS4C8M16D1-5TIN, the AS4C16M16D1-5TIN, and the AS4C32M16D1-5TIN are high-speed CMOS double data rate synchronous DRAMs (DDR SDRAMs). The devices feature densities of 64 MB (AS4C4M16D1-5TIN), 128 MB (AS4C8M16D1-5TIN), 256 MB (AS4C16M16D1-5TIN), and 512 MB (AS4C32M16D1-5TIN) with a –40°C to 85°C industrial temperature range.

The DDR SDRAMs provide reliable drop-in, pin-for-pin-compatible replacements for industrial, medical, communications, and telecommunications products requiring high memory bandwidth. The devices are well-suited for high performance in PC applications. Internally configured as four banks of 1M, 2M, 4M, or 8M word × 16 bits with a synchronous interface, the DDR SDRAMs operate from a single 2.5-V (± 0.2 V) power supply and are lead- and halogen-free.

The AS4C4M16D1-5TIN, the AS4C8M16D1-5TIN, the AS4C16M16D1-5TIN, and the AS4C32M16D1-5TIN feature a 200-MHz clock rate and are available in a 66-pin TSOP II package with a 0.65-mm pin pitch. The 128-, 256-, and 512-MB devices are also available in a TFBGA package.

The DDR SDRAMs provide programmable read or write burst lengths of 2, 4, or 8. An auto pre-charge function provides a self-timed row pre-charge initiated at the end of the burst sequence. Easy-to-use refresh functions include auto- or self-refresh. A programmable mode register enables the system to choose a suitable mode for maximum performance.
Pricing for the AS4C4M16D1-5TIN, the AS4C8M16D1-5TIN, the AS4C16M16D1-5TIN, and the AS4C32M16D1-5TIN starts at $0.90 per piece.

Alliance Memory, Inc.
www.alliancememory.com

The Future of Very Large-Scale Integration (VLSI) Technology

The historical growth of IC computing power has profoundly changed the way we create, process, communicate, and store information. The engine of this phenomenal growth is the ability to shrink transistor dimensions every few years. This trend, known as Moore’s law, has continued for the past 50 years. The predicted demise of Moore’s law has been repeatedly proven wrong thanks to technological breakthroughs (e.g., optical resolution enhancement techniques, high-k metal gates, multi-gate transistors, fully depleted ultra-thin body technology, and 3-D wafer stacking). However, it is projected that in one or two decades, transistor dimensions will reach a point where it will become uneconomical to shrink them any further, which will eventually result in the end of the CMOS scaling roadmap. This essay discusses the potential and limitations of several post-CMOS candidates currently being pursued by the device community.

Steep transistors: The ability to scale a transistor’s supply voltage is determined by the minimum voltage required to switch the device between an on- and an off-state. The sub-threshold slope (SS) is the measure used to indicate this property. For instance, a smaller SS means the transistor can be turned on using a smaller supply voltage while meeting the same off current. For MOSFETs, the SS has to be greater than ln(10) × kT/q where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. This fundamental constraint arises from the thermionic nature of the MOSFET conduction mechanism and leads to a fundamental power/performance tradeoff, which could be overcome if SS values significantly lower than the theoretical 60-mV/decade limit could be achieved. Many device types have been proposed that could produce steep SS values, including tunneling field-effect transistors (TFETs), nanoelectromechanical system (NEMS) devices, ferroelectric-gate FETs, and impact ionization MOSFETs. Several recent papers have reported experimental observation of SS values in TFETs as low as 40 mV/decade at room temperature. These so-called “steep” devices’ main limitations are their low mobility, asymmetric drive current, bias dependent SS, and larger statistical variations in comparison to traditional MOSFETs.

Spin devices: Spintronics is a technology that utilizes nano magnets’ spin direction as the state variable. Spintronics has unique properties over CMOS, including nonvolatility, lower device count, and the potential for non-Boolean computing architectures. Spintronics devices’ nonvolatility enables instant processor wake-up and power-down that could dramatically reduce the static power consumption. Furthermore, it can enable novel processor-in-memory or logic-in-memory architectures that are not possible with silicon technology. Although in its infancy, research in spintronics has been gaining momentum over the past decade, as these devices could potentially overcome the power bottleneck of CMOS scaling by offering a completely new computing paradigm. In recent years, progress has been made toward demonstration of various post-CMOS spintronic devices including all-spin logic, spin wave devices, domain wall magnets for logic applications, and spin transfer torque magnetoresistive RAM (STT-MRAM) and spin-Hall torque (SHT) MRAM for memory applications. However, for spintronics technology to become a viable post-CMOS device platform, researchers must find ways to eliminate the transistors required to drive the clock and power supply signals. Otherwise, the performance will always be limited by CMOS technology. Other remaining challenges for spintronics devices include their relatively high active power, short interconnect distance, and complex fabrication process.

Flexible electronics: Distributed large area (cm2-to-m2) electronic systems based on flexible thin-film-transistor (TFT) technology are drawing much attention due to unique properties such as mechanical conformability, low temperature processability, large area coverage, and low fabrication costs. Various forms of flexible TFTs can either enable applications that were not achievable using traditional silicon based technology, or surpass them in terms of cost per area. Flexible electronics cannot match the performance of silicon-based ICs due to the low carrier mobility. Instead, this technology is meant to complement them by enabling distributed sensor systems over a large area with moderate performance (less than 1 MHz). Development of inkjet or roll-to-roll printing techniques for flexible TFTs is underway for low-cost manufacturing, making product-level implementations feasible. Despite these encouraging new developments, the low mobility and high sensitivity to processing parameters present major fabrication challenges for realizing flexible electronic systems.

CMOS scaling is coming to an end, but no single technology has emerged as a clear successor to silicon. The urgent need for post-CMOS alternatives will continue to drive high-risk, high-payoff research on novel device technologies. Replicating silicon’s success might sound like a pipe dream. But with the world’s best and brightest minds at work, we have reasons to be optimistic.

Author’s Note: I’d like to acknowledge the work of PhD students Ayan Paul and Jongyeon Kim.

Can MoS2 Outperform Silicon?


Saptarshi Das

After decades of relentless progress, the evolutionary path of the silicon CMOS industry is finally approaching an end. Fundamental physical limitations do not enable silicon to scale beyond the 10-nm technology node without severely compromising a device’s performance. To reinforce the accelerating pace, there is an urgent and immediate need for alternative materials. Low-dimensional materials in general, and 2-D layered material in particular, are extremely interesting in this context. They offer unique electrical, optical, mechanical, and chemical properties. In addition, they feature excellent electrostatic integrity and inherent scalability, which makes them attractive from a technological standpoint. Graphene, hexagonal boron nitride (h-BN), and more recently the rich family of transition metal dichalcogenides—comprising Molybdenum disulfide (MoS2), WS2, WSe2, and many more—have received a lot of scientific attention as the future of nanoelectronics. The most widely studied material, grapheme, had reported intrinsic field effect mobility value as high as 10,000 cm2/Vs. However, the absence of an energy gap in the electronic band structure of grapheme, along with the challenges associated with making a stable interface with the gate dielectric, raises a lot of concern for grapheme-based nanoelectronics for logic applications. Hence, it paves the way for semiconducting 2-D materials such as MoS2 and others.

MoS2 is a stack of single layers held together by weak van der Waals interlayer interaction, and, therefore, enables micromechanical exfoliation of one or a few layers—similar to the fabrication of graphene from graphite. It is a semiconductor with an indirect bandgap of 1.2 eV. Single- and multilayer MoS2 field-effect transistors (FETs) with high on/off-current ratios (108) and excellent subthreshold swing (74 mV/decade) close to the ideal limit have been demonstrated. Basic integrated circuits (e.g., inverters and ring oscillators) have been reported. And initial studies also indicate that MoS2 has great potential in future nanoelectronics, sensing, and energy harvesting.

While there is a growing interest in MoS2-based nanoelectronics devices, the practice of evaluating their potential usefulness for electronic applications is still in its infancy since we don’t have a complete picture of their performance potential and scaling limits. My research addresses the major issues about the realization of high-performance logic devices based on ultra-thin MoS2 flakes. One of the major challenges in the realization of high-performance nano devices arises from the fact that these nanostructures need to be connected to the “outside” world to capitalize on their ultimate potential. Any interface between a low-dimensional nanostructure and a 3-D metal contact will inevitably affect the total system’s performance, which will strongly depend on the said contact’s quality. We have demonstrated that through a proper understanding and design of source/drain contacts and the right choice of the number of MoS2 layers to use, the excellent intrinsic properties of this 2-D material can be realized. Using scandium contacts on 10-nm-thick exfoliated MoS2 flakes that are covered by a 15-nm Al2O3 film, record high mobilities of 700 cm2/Vs are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. We have also investigated the ultimate scaling potential of multilayer MoS2 field effect transistors (FETs) with channel lengths ranging from 1 µm down to 50 nm. Our results indicate that the multilayer MoS2 FETs are extremely resilient to short channel effects. We have demonstrated record high drive current density of 2.5 mA/µm and record high transconductance of 500 µs/µm for a 50-nm-long MoS2 transistor, which are comparable to state-of-the-art silicon technology.

In short, MoS2 preserves all the important properties of silicon with the added advantage of an ultra-thin layer structure, which allows for aggressive channel length scaling down to 2 nm and, therefore, has the potential to outperform silicon beyond the 10-nm technology node. Properly nourishing the development of MoS2 can be a real game changer for the future of the micro- and nanoelectronics industry.—by Saptarshi Das, Circuit Cellar 270, January 2012

DIY Solar-Powered, Gas-Detecting Mobile Robot

German engineer Jens Altenburg’s solar-powered hidden observing vehicle system (SOPHECLES) is an innovative gas-detecting mobile robot. When the Texas Instruments MSP430-based mobile robot detects noxious gas, it transmits a notification alert to a PC, Altenburg explains in his article, “SOPHOCLES: A Solar-Powered MSP430 Robot.”  The MCU controls an on-board CMOS camera and can wirelessly transmit images to the “Robot Control Center” user interface.

Take a look at the complete SOPHOCLES design. The CMOS camera is located on top of the robot. Radio modem is hidden behind the camera so only the antenna is visible. A flexible cable connects the camera with the MSP430 microcontroller.

Altenburg writes:

The MSP430 microcontroller controls SOPHOCLES. Why did I need an MSP430? There are lots of other micros, some of which have more power than the MSP430, but the word “power” shows you the right way. SOPHOCLES is the first robot (with the exception of space robots like Sojourner and Lunakhod) that I know of that’s powered by a single lithium battery and a solar cell for long missions.

The SOPHOCLES includes a transceiver, sensors, power supply, motor
drivers, and an MSP430. Some block functions (i.e., the motor driver or radio modems) are represented by software modules.

How is this possible? The magic mantra is, “Save power, save power, save power.” In this case, the most important feature of the MSP430 is its low power consumption. It needs less than 1 mA in Operating mode and even less in Sleep mode because the main function of the robot is sleeping (my main function, too). From time to time the robot wakes up, checks the sensor, takes pictures of its surroundings, and then falls back to sleep. Nice job, not only for robots, I think.

The power for the active time comes from the solar cell. High-efficiency cells provide electric energy for a minimum of approximately two minutes of active time per hour. Good lighting conditions (e.g., direct sunlight or a light beam from a lamp) activate the robot permanently. The robot needs only about 25 mA for actions such as driving its wheel, communicating via radio, or takes pictures with its built in camera. Isn’t that impossible? No! …

The robot has two power sources. One source is a 3-V lithium battery with a 600-mAh capacity. The battery supplies the CPU in Sleep mode, during which all other loads are turned off. The other source of power comes from a solar cell. The solar cell charges a special 2.2-F capacitor. A step-up converter changes the unregulated input voltage into 5-V main power. The LTC3401 changes the voltage with an efficiency of about 96% …

Because of the changing light conditions, a step-up voltage converter is needed for generating stabilized VCC voltage. The LTC3401 is a high-efficiency converter that starts up from an input voltage as low as 1 V.

If the input voltage increases to about 3.5 V (at the capacitor), the robot will wake up, changing into Standby mode. Now the robot can work.

The approximate lifetime with a full-charged capacitor depends on its tasks. With maximum activity, the charging is used after one or two minutes and then the robot goes into Sleep mode. Under poor conditions (e.g., low light for a long time), the robot has an Emergency mode, during which the robot charges the capacitor from its lithium cell. Therefore, the robot has a chance to leave the bad area or contact the PC…

The control software runs on a normal PC, and all you need is a small radio box to get the signals from the robot.

The Robot Control Center serves as an interface to control the robot. Its main feature is to display the transmitted pictures and measurement values of the sensors.

Various buttons and throttles give you full control of the robot when power is available or sunlight hits the solar cells. In addition, it’s easy to make short slide shows from the pictures captured by the robot. Each session can be saved on a disk and played in the Robot Control Center…

The entire article appears in Circuit Cellar 147 2002. Type “solarrobot”  to access the password-protected article.