New CPU Core Boosts Performance for Renesas MCUs

Renesas Electronics has announced the development of its third-generation 32-bit RX CPU core, the RXv3. The RXv3 CPU core will be employed in Renesas’ new RX microcontroller families that begin rolling out at the end of 2018. The new MCUs are designed to address the real-time performance and enhanced stability required by motor control and industrial applications in next-generation smart factory, smart home and smart infrastructure equipment.

The RXv3 core boosts CPU core architecture performance with up to 5.8 CoreMark/MHz, as measured by EEMBC benchmarks, to deliver industry-leading performance, power efficiency and responsiveness. The RXv3 core is backwards compatible with the RXv2 and RXv1 CPU cores in Renesas’ current 32-bit RX MCU families. Binary compatibility using the same CPU core instruction sets ensures that applications written for the previous-generation RXv2 and RXv1 cores carry forward to the RXv3-based MCUs. Designers working with RXv3-based MCUs can also take advantage of the robust Renesas RX development ecosystem to develop their embedded systems.
The RX CPU core combines a design optimized for power efficiency and a fabrication process producing excellent performance. The new RXv3 CPU core is primarily a CISC (Complex Instruction Set Computer) architecture that offers significant advantages over the RISC (Reduced Instruction Set Computer) architecture in terms of code density. RXv3 utilizes a pipeline to deliver high instructions per cycle (IPC) performance comparable to RISC. The new RXv3 core builds on the proven RXv2 architecture with an enhanced pipeline, options for register bank save functions and double precision floating-point unit (FPU) capabilities to achieve high computing performance, along with power and code efficiency.

The enhanced RX core five-stage superscalar architecture enables the pipeline to execute more instructions simultaneously while maintaining excellent power efficiency. The RXv3 core will enable the first new RX600 MCUs to achieve 44.8 CoreMark/mA with an energy-saving cache design that reduces both access time and power consumption during on-chip flash memory reads, such as instruction fetch.

The RXv3 core achieves significantly faster interrupt response times with a new option for single-cycle register saves. Using dedicated instruction and a save register bank with up to 256 banks, designers can minimize the interrupt handling overhead required for embedded systems operating in real-time applications such as motor control. RTOS context switch time is up to 20 percent faster with the register bank save function.

The model-based development (MBD) approach has penetrated various application developments; it enables the DP-FPU to help reduce the effort of porting high precision control models to the MCU. Similar to the RXv2 core, the RXv3 core performs DSP/FPU operations and memory accesses simultaneously to substantially boost signal processing capabilities.

Renesas plans to start sampling shipments of RXv3-based MCUs before the end of Q4 2018.

Renesas Electronics | www.renesas.com

Benchmarks for the IoT

Input Voltage

–Jeff Child, Editor-in-Chief

JeffHeadShot

I remember quite vividly back in 1997 when Marcus Levy founded the Embedded Microprocessor Benchmark Consortium, better known as EEMBC. It was big deal at the time because, while benchmarks where common in the consumer computing world of desktop/laptop processors, no one had ever crafted any serious benchmarks for embedded processors. I was an editor covering embedded systems technology at the time, and Marcus, as an editor with EDN Magazine back then, traveled in the same circles as I did. On both the editorial side and on the processor vendor side, he had enormous respect in the industry—making him an ideal person to spin up an effort like EEMBC.

Creating benchmarks for embedded processors was more complicated than for general purpose processors, but EEMBC was up the challenge. Fast forward to today, and EEEBC now boasts a rich list of performance benchmarks for the hardware and software used in a variety of applications including autonomous driving, mobile imaging, mobile devices and many others. In recent years, the group has taken on the complex challenge of developing benchmarks for the Internet-of-Things (IoT).

I recently had the chance to talk with EEMBC’s current president, Peter Torelli, about the consortium’s latest effort: its IoTMark-BLE benchmark. It’s part of the EEMBC’s IoTMark benchmarking suite for measuring the combined energy consumption of an edge node’s sensor interface, processor and radio interface. IoTMark-BLE focuses on Bluetooth Low Energy (BLE) devices. In late September, EEMBC announced that the IoTMark-BLE benchmark is available for licensing.

The IoTMark-BLE benchmark profile models a real IoT edge node consisting of an I²C sensor and a BLE radio through sleep, advertise and connected-mode operation. The benchmark measures the energy required to power the edge node platform and to run the tests fed by the benchmark. At the center of the benchmark is the IoTConnect framework, a low-cost benchmarking harness used by multiple EEMBC benchmarks. The framework provides an external sensor emulator (the I/O Manager), a BLE gateway (the radio manager) and an Energy Monitor.

Benchmark users interact with the DUT via an interface with which they can set a number of tightly defined parameters, such as connection interval, I²C speed, BLE transmission power and more. Default values are provided to enable direct comparisons between DUTs, or users can change them to analyze a design’s sensitivity to each parameter. IoTMark-BLE’s IoTConnect framework supports microcontrollers (MCUs) and radio modules from any vendor, and it is compatible with any embedded OS, software stack or OEM hardware.

It makes sense that IoT benchmarks focus on power and energy use. IoT edge devices need to work in remote locations near the sensors they’re linked with. With that in mind, Peter Torelli says that the benchmark measures everything inside an IoT system-on-chip (SoC)—including the peripheral I/O reading from the I2C sensor, the transmit and receive amplifiers in the BLE radio—everything except the sensor itself. Torelli says it was important to not use intelligent sensors for the benchmark, the idea being that its important that the MCU’s role performing communication be part of the measurement. Interestingly, in developing the benchmark, it was found that even the software stacks on IoT SoCs have a big impact on performance. “Some are very efficient when they’re in advertise mode or in active mode, and then go to sleep,” says Torelli, “And there are others that remain active for much longer times and burn a lot of power.”

Shifting gears, I want to take moment to praise long time columnist and member of the Circuit Cellar family, Ed Nisley. Over 30 years ago, Steve Ciarcia asked Ed to write a regular column for the brand-new Circuit Cellar INK magazine. After an even 200 articles, Ed decided to make his September column his last. Thank you, Ed, for your many years of insightful, quality work in the pages of this magazine. You’ll be missed. Readers can follow Ed’s continuing series of shop notes, projects and curiosities on his blog at softsolder.com.

Let me welcome Brian Millier as our newest Circuit Cellar columnist—his column Pickup Up Mixed Signals begins this issue. Brian is no stranger to the magazine, penning over 50 guest features in the magazine since the mid-90s on a variety of topics including guitar amplifier electronics, IoT system design, LCDs and many others. I’m thrilled to have Brian joining our team. With his help, we promise to continue fulfilling Circuit Cellar’s role as the leading media platform aimed at inspiring the evolution of embedded system design.

This appears in the November 340 issue of Circuit Cellar magazine

Not a Circuit Cellar subscriber?  Don’t be left out! Sign up today:

EEMBC Releases SecureMark-TLS Benchmark for IoT Devices

EEMBC, an industry consortium that develops benchmarks for embedded hardware and software, today announced that its SecureMark-TLS benchmark is now available for licensing. Part of the SecureMark benchmarking suite for measuring the efficiency of cryptographic processing solutions, SecureMark-TLS focuses on the Transport Layer Security (TLS) protocol for internet of things (IoT) edge nodes.

SecureMark-TLS measures the performance and energy consumption of processors when implementing the TLS protocol on an edge device. The benchmark uses a common IoT cypher suite comprised of elliptic curve cryptography for key exchange and digital signing, and standard primitives such as SHA256 and AES128, in both CCM and ECB modes. The energy measurements are aggregated into a single final score that is representative of the TLS operations for the IoT edge node device.

“While security has become a paramount concern, implementing security comes at a price. SecureMark-TLS is intended to help system and silicon designers evaluate the performance and energy costs of implementing security,” said Jim McGregor, principal analyst at TIRIAS Research. “By using the most common encryption protocol for IoT edge nodes, SecureMark-TLS provides a new metric for comparing processors and SoCs.”

Other differentiators between products, such as cryptographic certifications (e.g., NIST or Common Criteria), countermeasures (xPA, fault injection), and hardware implementation specifics, can be described in a disclosure report. The disclosure report also includes a description of all relevant implementation details, such as the hardware device tested, the software library version used, compiler options and flags, and hardware crypto engine details if applicable.

“EEMBC’s SecureMark suite is designed to provide an industry-created and standardized tool that allows applications developers to analyze security implementations,” said Peter Torelli, EEMBC president and CTO. “Within the suite, we plan to support the testing and analysis of various security profiles for different application domains. For secure IoT communication, we are proud to introduce SecureMark-TLS as the first of these available for licensing.”

To request a SecureMark-TLS license, visit
https://eembc.org/memberinfo/requestinfo.php?reg=LIC&suite=securemark

EEMBC | www.eembc.org

High-Performance MCUs Serve IoT Device Needs

STMicroelectronics has added two new lines to its STM32 MCU family, the STM32F7x0 and H7x0 Value Line. The MCUs are aimed at enabling system designers to create affordable performance-oriented systems including real-time IoT devices, without compromising features or cyber protection.

These new lines trim embedded flash to the essential, still allowing secure boot, sensitive code and real-time routines to run safely on-chip, leveraging access times over 25 times faster than for external Flash (for cache miss). If needed, applications can scale-up either by adding off-chip serial or parallel (up to 32-bit) memories and leveraging the MCUs’ broad external interfaces and eXecute in Place (XiP) capability, or by porting to other pin-to-pin compatible STM32F7 or STM32H7 MCU lines, with up to 2 MB Flash and up to 1 MB RAM, supported by the same ecosystem with the same easy-to-use tools.

The Value Lines retain powerful STM32F7 and H7 features, such as the state-of-the-art peripherals, hardware accelerators, and the real-time architecture with ultra-fast internal buses, short interrupt latency, and fast (approximately 1 ms) boot-up. The MCUs are also energy efficient, with flexible power modes, gated power domains, and on-chip power management that simplify design and reduce BOM cost.

With execution performance up to 2020 CoreMark at the heart of a secure and power-efficient architecture, the new Value Line devices are the entry point to IoT innovation in medical, industrial, and consumer applications. CoreMark is the EEMBC standardized benchmark for embedded-CPU performance. With up to 125°C as the maximum junction temperature, developers can leverage the full core and peripherals performance even when ambient temperature increases.

The entry-level STM32F730 delivers 1082 CoreMark performance running at 216MHz aided by ST’s unique ART Accelerator for zero-wait-state execution from Flash. Features include cryptographic hardware acceleration, a USB 2.0 High Speed port with PHY, and a CAN interface. There is a 64Kbyte Flash, 8KByte Instruction and data caches for high-performance execution from internal or external memories, 256KB of system RAM and 16 KB plus 64 KB of Tightly Coupled Memory (TCM) for the most critical routines and data.

The STM32F750 adds a TFT-LCD controller with ST’s proprietary Chrom-ART Graphics Accelerator. It has hardware acceleration for hash algorithms, two CAN interfaces, an Ethernet MAC, camera interface, and two USB 2.0 interfaces with Full Speed PHY. There are 64Kbytes of Flash, 4Kbyte instruction and 4 KB data caches, 320 KB of system RAM and 16 KB plus 64 KB TCM.

The high-end STM32H750 delivers 2020 CoreMark performance at 400 MHz and adds a hardware JPEG coder/decoder to the TFT controller and Chrom-ART Accelerator for even faster GUI performance. There is also a CANFD port and additional CANFD with time-trigger capability and best-in-class operational amplifiers and 16-bit ADCs running at up to 3.6 Msample/s. The 128 KB flash, 16 KB instruction and data caches, 864 KB system RAM and the 64 KB+128 KB of TCM all feature ECC (Error Correction Code) for safe execution from internal or external memory.

The STM32F730, STM32F750, and STM32H750 Value Line MCUs are in production, in various LQFP and BGA package options from 64-pin to 240-pin. Prices start from $1.64 for the STM32F730, $2.39 for the STM32F750 and $2.69 for the STM32H750 for orders of 1,000 pieces.

STMicroelectronics | www.st.com