I can capture repetitive waveforms at 1 Msps using a microcontroller’s on-chip PWM and comparator. The impetus for developing this technique came from my own need to capture repetitive waveforms using the least expensive and lowest part count means possible. I wanted to be able to view the waveforms on an LCD dedicated to the purpose or upload the waveform to a computer for manipulation on a spreadsheet. This waveform capture method adheres to the “minimum mass” product design concept: it doesn’t use anything that is not absolutely essential to obtaining the needed function.
Implementations can be cheap enough to allow capture and analysis in many applications that otherwise could not justify the cost. Such applications include calculating the RMS values or harmonic content of waveforms for power management and equipment maintenance, self-testing audio frequency circuits, the analysis of pulse response for self-tuning servos, signal signature analysis, and remote diagnostics and data gathering.
The approaches using on-chip A/D converters on AVR and PIC controllers reach sample rates of up to nearly 60 kHz. Exotic and pricey high-speed controllers top out around 100 kHz. Such a sampling rate is not really high enough for the sort of applications I had in mind: encoded data, radio control signals, A/D converter waveforms, checking the dynamic range of amplifiers and capturing audio frequency waveforms for filtering, and power calculations. I realized that the comparators in AVR and PIC devices have fast response times (several hundred nanoseconds) and that the pulse width modulation (PWM) circuit could be made fairly responsive. I just needed some way to quickly combine them to sample analog values.
Eventually it became apparent that repetitive sampling was the only way to get high enough voltage and temporal sampling resolution using only these on-chip components. Rather than trying to sample and digitize the waveform in real time as it comes in, this method finds out a little bit about the waveform using the relatively high-speed comparator every time the waveform is repeated; it builds a more detailed picture with each repetition by changing the relatively low-speed PWM voltage each time.
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To capture a waveform, the PWM D/A converter (PWM DAC) is set to its maximum output voltage. Then, using timing loops to generate regularly spaced sampling times (1 µs in Figure 1), the microcontroller looks at the output of the voltage comparator to determine if the incoming voltage is higher than the PWM voltage. At each sampling time, if the PWM voltage is at a higher voltage than that of the incoming waveform, the PWM value is stored in a RAM array location corresponding to that sampling time.
Figure 1—It’s all in the timing. Firmware timing loops set the interval between samples in a burst of waveform samplings that starts with a trigger signal. The green dots represent voltage levels of the sampled signal at the time of sampling.
After all of the sample times have been tested against the PWM voltage, the PWM voltage is decremented. The process is then repeated until the PWM voltage has been reduced to its minimum value (0 V). Each scan of the sample time starts by a trigger signal that’s derived from, or in some way related to, the incoming waveform. The finer the voltage resolution, the longer it takes to capture the waveform because the waveform has to be sampled more times. Note that the settling time for the PWM DAC needs to be longer for finer voltage resolution.
The total capture time (TCAP) equals: the number of voltage levels × (trigger latency + sample time + step settling time). Trigger latency is the average amount of time the controller waits for a trigger signal. The initial PWM settling time and the step settling time are the times for the PWM filter to charge to its initial value and settle after a 1-LSB step change, respectively. Capturing 100 samples at 1 Msps in a circuit optimized for 6-bit resolution (64 levels) takes approximately 69 ms; however, it takes about 1.3 s to measure the same waveform on a circuit optimized for 8-bit resolution.
When capturing waveforms with long periods, the total time needed to capture the waveform is dominated by the time it takes the waveform to make the requisite number of repetitions. For shorter periods, the total time is dominated by the settling times for the PWM. Thus, the higher the sampling rate, the more you can speed up the capture cycle by using a faster DAC. A resistor network connected to some port pins could suffice for low-resolution (6-bit) waveform capture. An integrated circuit DAC would be better for higher resolution applications.
The quality of the trigger signal is essential to the fidelity of the captured waveform. The trigger signal must consistently appear at the same time with respect to the captured signal, otherwise severe distortion will result. This means that a noisy trigger signal, such as one derived directly from a noisy input signal, would give poor results. You’ll get the best results with a digital trigger signal taken directly from the source of the signal if such a trigger source is available.
Unsynchronized signals (e.g., noise) are not represented accurately; instead, such signals are underrepresented in the captured waveform. This quality, which results from synchronous sampling, is sometimes a good thing because it can effectively pull a signal out of the noise, which is an important property in applications such as ultra wideband and spread-spectrum signal decoding. But, if you intend to measure noise or jitter, this quality makes the system inappropriate.
Another aspect of sampled data systems is their susceptibility to aliasing. Aliasing is a phenomenon in which a signal appears to occur at a frequency other than that at which it actually occurs. For instance, when a 250-kHz square wave is viewed with a 1-µs sampling interval, it shows up properly as four samples per cycle; however, when it is captured at a 100-µs sampling interval, it appears as 16 samples per cycle, or a 625-Hz signal, which is one four-hundredth the actual frequency.
To prevent aliasing, insert an analog filter in the signal path before the comparator’s input. In the example I’ve been focusing on, the Atmel AT90S2313 samples the signal at 1 Msps. The on-chip comparator has a propagation delay of 500 to 700 ns, providing inherent filtering for components of signals above approximately 800 kHz, and thus restricting the range of frequencies above the sampling rate that can be aliased down to frequencies below the sampling rate. To reduce the aliasing of signal components that have a lower frequency than the sampling rate, you’d need an additional external analog filter.
Figure 2—You can work with a bare minimum of parts, because it doesn’t take much to capture repetitive waveforms at 1 Msps and upload them to a terminal program on a PC for display and analysis. The passive components connected to pins 13 and 15 of the microcontroller are in the same basic configuration used for successive approximation A/D conversion; only the firmware is different.
The simple implementation shown in Figure 2 needs only a microcontroller with a DAC and voltage comparator, and some way to get control signals into the chip and the data back out. The demonstration system, for which firmware is posted on the Circuit Cellar ftp site, assumes an Atmel AT90S231310 is connected to level-shifting inverters for the EIA-232 interface such as a Maxim MAX232 with its 1-µf capacitors, a 10-MHz crystal with load capacitors, a decoupling capacitor, and the PWM low-pass filter connected to pins 13 and 15 of the microcontroller (see Photo 1).
Photo 1—The only components added to the operating Atmel AT90S2313 circuit needed to allow for waveform sampling with less than 1-μs resolution at 1-V full scale are the capacitor and two resistors. Imagine how small the circuit will be using surface-mount components.
It can be controlled by and dump data to an ASCII terminal program such as HyperTerminal at capture rates from 1 µs per sample to 10 ms per sample at 6-, 7-, and 8-bit resolution with selectable trigger polarity. An example of a waveform captured with this system and plotted in a spreadsheet program is shown in Figure 3.
Figure 3—This is the capture of a 31.25-kHz sawtooth waveform. The sample rate is set to 1 μs per sample and the voltage resolution is 8 bits.
PWM LOW-PASS FILTER
The DAC uses pulse-width modulation, so it is necessary to have an averaging (low-pass) filter to recover the DC component while filtering out most of the PWM signal’s AC component. The AC component remaining on the filter’s output is referred to as ripple.
The filter is made up of 330- and 82-kΩ resistors and a 0.047-µF capacitor, which forms a single-pole RC filter. The two resistors form a voltage divider to reduce the full-scale voltage from the DAC to 1-V full scale. If you are worried about accuracy, you can replace the 82-kΩ resistor with a fixed resistor and a variable resistor in series to allow for full-scale calibration.
If 5-V full scale is appropriate for your application, you can omit the lower resistor and save a part. The low-pass filter for the PWM output needs to be made with a large enough time constant to keep the ripple to an acceptable level. After the filter time constant is pinned down, the controller must wait long enough after each step change in output voltage for the filter to settle adequately before starting measurements.
The PWM filter can be analyzed as a single resistor driving the capacitor (see Figure 4). Judging from the AT90S2313 datasheet, when operating at 5 V, the output resistance of the PWM output is approximately 28 Ω; it is safe to say that it is negligible compared to the 330-kΩ resistor that’s in series with it. Thus, the filter model is plenty close by taking the value of the resistance to be the parallel combination of the two resistors (see Figure 4).
Figure 4—The PWM filter is easily analyzed as a single resistor charging the capacitor by replacing the resistors with a single resistor equal to the parallel combination of the two, because that is what it looks like to the capacitor.
The first step is to select the time constant that gives an acceptably low ripple. For my application, I considered speed to be more important than absolute accuracy, so I decided to keep the ripple at 1 LSB. The time constant should be figured for the worst possible PWM signal. The worst case for ripple is when the lowest frequency appears at the filter’s input. In the case of the AT90S2313, this occurs when the PWM output runs 50% duty cycle. Under this condition, the pulse frequency is about 19.6 kHz and the voltage across the capacitor is 0.5 V. When the pulse is high (this analysis is the same for the time the pulse is low, only the signs change), the difference between the PWM peak voltage (1 V) and the voltage across the capacitor is across the equivalent resistance, and the current through the resistance charges the capacitor.
Note that 1 LSB of an 8-bit value based on 1-V full scale is 4 mV (1/255). Using the formula in Figure 5, the time constant must be approximately 3.2 ms. I chose the resistors by first selecting the largest capacitor and a pair of large resistors that had the necessary 4:1 resistance ratio while simultaneously giving nearly the correct time constant. The resulting combination gives a divide ratio of 1:5.02 and a time constant of 3.15 ms (67 kΩ × 0.047 µF).
Figure 5—A simplified model can be used to predict the relationship between the filter’s time constant and the amount of ripple. The charging current for the capacitor comes from the voltage drop between the 1 V from the output of the resistive divider and the voltage across the capacitor. Note that EO is the voltage change across the capacitor (1 LSB = 4 mV), and EI is the average voltage across the resistance (0.5 V). T is the time that voltage is applied across the circuit (25.5 μs), and t is the time constant of the circuit.
After the filter time constant is known, the settling times can be determined. I decided to have the controller wait for the initial settling of the filter to within 1 LSB of full scale before starting the waveform capture cycle using the formula in Figure 6. For the settling time between successive steps, I wanted to wait until after the voltage changed more than 0.5 LSB. Because the step size is 1 LSB, I chose one time constant, or 3 ms.
Figure 6—The initial settling time must be long enough to assure that the PWM output settles to within 1 LSB of the final voltage. It must be calculated for the worst case scenario, which is when it starts from 0 V. Note that ΔV is the error in the settled voltage (1 LSB = 4 mV). EI is the voltage applied to the circuit, which is 1 V. In is the natural logarithm (base 2.71828…). T is the time that voltage is applied across the circuit, and t is the time constant of the circuit (3.17 ms).
When capturing a waveform, the PWM circuit first generates the maximum output voltage and samples all time intervals starting from a trigger signal, taking care to keep the time between samples constant. Whenever the voltage at a sampled time exceeds the PWM voltage, the PWM value is stored in the RAM array location corresponding to that sample. In this way, at the end of the capture cycle, the peak value at each sampling time is stored in the RAM array.
The sampling loop in Listing 1 is the time-critical part of the code. It requires 10 clock cycles per sample. With a 10-MHz clock, the sampling rate is 1 MHz. Two clock cycles are taken up by the indirect jump instruction (ijmp), which jumps either to the next instruction in sequence (at the label oneus:) or to a delay routine that returns to the next instruction in sequence. Eliminating the indirect jump instruction would decrease the sampling interval to eight cycles. Straight line coding would be inflexible and take a lot of program memory, but it could reduce the sampling interval to as few as three cycles when storing the waveform in RAM.
Listing 1—The sampling of the waveform takes place at the sbic ACSR,5 instruction, where the output of the comparator is tested. If the comparator’s output is low, execution proceeds to st Y+,pwmval, the instruction that stores the data into the RAM array via the Y pointer. If the comparator’s input is high, the program branches back to nextydelay, which imcrements the Y pointer without storing data.
At the beginning of a waveform collection cycle, the program sits in a wait loop and waits for a transition on the trigger input. After the triggering edge is detected, the sampling routine is called and it runs through and collects a full set of samples. Then, the PWM value is decremented, a wait loop is executed to allow the RC filter in the PWM DAC to settle, and the program returns to wait for the next triggering event. This process continues until the lowest possible PWM value has been tested.
Timing uncertainty is introduced by the short loop in which the controller waits for the triggering edge. The uncertainty translates into jitter in the signal sampling. As long as the uncertainty is small compared to the signal-sampling interval, it should not contribute much in the way of noise to the captured waveform. In applications that use only a few machine cycles between samples, it pays to keep the wait loops as short as possible.
BELOW GROUND SIGNALS
Judging from the offset-versus-input voltage curve on the AT90S2313’s datasheet, the comparator’s differential gain is good enough for 6-bit waveform capture just above ground. For linearity errors of less than 1 LSB with 8-bit operation, the comparator inputs need to run closer to the middle of the power supply where the curve is nearly flat.
There is a bonus to adding offset to the input signal in that it can measure input signals at and below ground without clipping. When the input signal is level-shifted, the PWM DAC’s output must be similarly offset. The PWM offset circuit provides an opportunity for an adjustable vertical-centering control (to use the oscilloscope term). Circuits that shift the input level and allow offset adjustment are shown in Figure 7.
Figure 7—The FET provides an offset allowing the input to swing above and below ground as well as moving the input to the AT90S2313’s on-chip comparator away from ground and enabling an offset adjustment. You can also achieve these functions with op-amps, but there are several trade-offs to consider.
Level shifting is achieved easily enough with an op-amp if you have a negative power supply, but my objective was to make the entire system operate from a single 5-V regulator. Besides, my cheap single-supply op-amps, which also had adequate dynamic range, had too poor a slew rate to give satisfactory performance at 1 Msps.
A junction field effect transistor (JFET) source follower is an ideal way to offset the input signal to a more positive voltage without much attenuation or loss of bandwidth. I used an MPF102 in my own circuit because I had some on hand. Numerous other small signal JFETs would work well.
Pinch-off voltage is the FET parameter that most affects the offset because, for most FETs, this parameter varies widely. To obtain the approximate 2.5-V offset (the DC voltage on the FET source when the gate is grounded), you can hand select an FET, adjust the source resistor (15 kΩ in the circuit above), or try a combination of the two. The higher the value of the resistor, the higher the offset voltage (i.e., up to nearly the pinch-off voltage of the FET, which is usually specified at a low current). Be aware that the source resistor affects the trade-off between the bandwidth and signal loss. As the resistor gets larger, the bandwidth will decrease; as the resistor gets smaller, the gain of the source follower drops. For my particular circuit layout and its parasitic capacitance, 15 kΩ was about the upper limit for 1 Msps.
One way to add an adjustable DC offset to the output of the PWM circuit without affecting the RC filter’s response time is to use an adjustable constant current source. The current source shown in Figure 7 relies on the fact that the 2N2907’s collector current is nearly equal to the emitter current. (The collector current equals the emitter current times Alpha, which is nearly unity and pretty stable.) Emitter current is determined by the voltage across the 8.2-kΩ emitter resistor, which follows the base voltage and is temperature-compensated by the diode in series with the potentiometer.
SIMPLE, ECONOMICAL, FLEXIBLE
Among the variations that may be useful are programmable offset and gain controls, and a calibration function using only a few resistors and additional I/O pins. In multiple-chip systems, the time-dependent sampling task can be offloaded to a low-cost slave processor with little or no RAM that sends intermediate results to a host. The slave could be one of the cheapest eight-pin microcontrollers offered that has a suitable on-chip voltage comparator. The minimum mass waveform capture approach is a building block that produces a much faster sampling rate and costs less than conventional approaches using on-chip A/D converters.
I suspect that by now you have come up with some ideas of your own. It’s easy enough to put the sample system together, so why not give it a try?
ABOUT THE AUTHOR
Dick Cappels enjoys tinkering with and writing about analog circuits and microcontrollers. He has published several papers relating to electronic displays in computer systems, and is currently active in the Society for Information Display. Dick holds 17 U.S. patents.