Issue 286: EQ Answers

Question 1—A divider is a logic module that takes two binary numbers and produces their numerical quotient (and optionally, the remainder). The basic structure is a series of subtractions and multiplexers, where the multiplexer uses the result of the subtraciton to select the value that gets passed to the next step. The quotient is formed from the bits used to control the multiplexers, and the remainder is the result of the last subtraction.

If it is implemented purely combinatorially, then the critical path through all of this logic is quite long (even with carry-lookahead in the subtractors) and the clock cycle must be very slow. What could be done to shorten the clock period without losing the ability to get a result on every clock?

Answer 1—Pretty much any large chunk of combinatorial logic can be pipelined in order to reduce the clock period. This allows it to produce more results in a given amount of time, at the expense of increasing the latency for any particular result.

Divider logic is very easy to pipeline, and the number of pipeline stages you can use is fairly arbitrary. You could insert a pipeline register after each subtract-mux pair, or you might choose to do two or more subtract-mux stages per pipeline register You could even go so far as to pipeline the subtracts and the muxes separately (or even pipeline *within* each subtract) in order to get the fastest possible clock speed, but this would be rather extreme.

The more pipeline registers you use, the shorter the critical path (and the clock period) can be, but you use more resources (the registers). Also, the overall latency goes up, since you need to account for the setup and propagation times of the pipeline registers in the clock period (in addition to the subtract-mux logic delays). This gets multiplied by the number of pipeline stages in order to compute the total latency.

Question 2—On the other hand, what could be done to reduce the amount of logic required for the divider, giving up the ability to have a result on every clock?

 

Answer 2—If you don’t need the level of performance provided by a pipelined divider, you can computes the quotient serially, one bit at a time. You would just need one subtractor and one multiplexer, along with registers to hold the input values, quotient bits and the intermediate result.

You could potentially compute more than one bit per clock period using additional subtract-mux stages. This gives you the flexibility to trade off space and time as needed for a particular application.

Question 3—An engineer wanted to build an 8-MHz filter that had a very narrow bandwidth, so he used a crystal lattice filter like this:

EQ-fig1-CC287-June14

However, when he built and tested his filter, he discovered that while it worked fine around 8 MHz, the attenuation at very high frequencies (e.g., >80 MHz) was very much reduced. What caused this?

Answer 3—The equivalent circuit for a quartz crystal is something like this:EQ-fig2-CC287-June14

The components across the bottom represent the mechanical resonance of the crystal itself, while the capacitor at the top represents the capacitance of the electrodes and holder. Typical values are:

  • Cser: 10s of fF (yes, femtofarads, 10-15F)
  • L: 10s of mH
  • R: 10s of ohms
  • Cpar: 10s of pF

The crystal has a series-resonant frequency based on just Cser and L. It has a relatively low impedance (basically just R) at this frequency.

It also has a parallel-resonant (sometimes called “antiresonant”) frequency when you consider the entire loop, including Cpar. Since Cser and Cpar are essentially in series, together they have a slightly lower capacitance than Cser alone, so the parallel-resonant frequency is slightly higher. The crystal’s impedance is very high at this frequency.

But at frequencies much higher than either of the resonant frequencies, you can see that the impedance of Cparalone dominates, and this just keeps decreasing with increasing frequency. This reduces the crystal lattice filter to a simple capacitive divider, which passes high freqeuncies with little attenuation.

Question 4—Suppose you know that a nominal 10.000 MHz crystal has a series-resonant frequency of 9.996490 MHz and a parallel-resonant frequency of 10.017730 MHz. You also know that its equivalent series capacitance is 27.1 fF. How can you calculate the value of its parallel capacitance?

Answer 4—First, calculate the crystal’s equivalent inductance, based on the series-resonant frequency:EQ-equation1-CC287-June14

Next, calculate the capacitance required to resonate with that inductance at the parallel-resonant frequency:EQ-equation2-CC287-June14

Finally, calculate the value of Cpar required to give that value of capacitance when in series with Cser:EQ-equation3-CC287-June14

Note that all three equations can be combined into one, and this reduces to:EQ-equation4-CC287-June14

Electrical Engineering Crossword (Issue 287)

The answers to Circuit Cellar’s April electronics engineering crossword puzzle are now available.

Crossword-CC286-May14

Across

1. BEAMFORMING—Signal processing technique

7. HETERODYNERECEIVER—Converts a signal to an intermediate frequency [two words]

8. AMIGA—A high-resolution PC based on Motorola’s 6800 microprocessor family

9. NAGLING—Creates “Russian doll”-type packets to improve a TCP/IP network’s performance

10. SERVERBLADE—A thin circuit board designed for one specific application [two words]

15. FUZZING—Tests for coding and security errors

17. PHASECHANGE—Nonvolatile RAM [two words]

18. WALLEDGARDEN—Restricts access to Web content and services [two words]

19. SERIALBACKPACK—A PCB interface that goes between a parallel LCD and a microcontroller [two words]

20. SLACKWARE—Open-source, Linux-based OS

Down

2. ROOTMEANSQUARE—Determines an AC wave’s voltage [three words]

3. ROENTGEN—IBM’s active matrix LCD

4. KERNELPANIC—Happens when a fatal error is detected [two words]

5. BIPHASEENCODING—Requires a state transition at the end of every data bit [two words]

6. PERMITTIVITY—Ability to be polarized

11. VOODOO—Helps create realistic 3-D graphics

12. FLANGING—An audio process that combines signals to create a comb filter effect

13. BREADBOARDING—Used for circuit design experimentation

14. STATOHM—Five of these equal approximately 4.5 × 1012

16. TELEDACTYL—Utilizes human speech to code

 

Electrical Engineering Crossword (Issue 286)

The answers to Circuit Cellar’s April electronics engineering crossword puzzle are now available.

Crossword-CC286-May14

Across

2. SAMBA—This networking protocol enables you to write to an embedded file system from a Windows PC

7. ELECTROMAGNETICFIELD—Used for data transfer [two words]

8. CAPACITOR—These types of microphones were commonly called “condensers” until about 1970

9. HOMODYNE—A receiver with direct amplification

13. BLENDER—Contains several modeling features and an integrated game engine

15. PULSESHAPING—Used to improve wired or wireless communication link performance [two words]

17. BRILLOUINSCATTERING—Occurs when certain types of light change their frequency and route [two words]

18. CLOCKSIGNAL—Used to coordinate circuits’ actions [two words]

19. RASPBERRYPI—Designed to encourage scholastic computer science lessons [two words]

Down

1. NONRETURNTOZERO—Typically 1s are a positive voltage and 0s are a negative voltage [four words]

3. BITARRAY—Provides compact storage for computing and digital communications [two words]

4. DOUBLEDATARATE—Coordinates the rising and falling edges of an [18 Across] to transfer data [three words]

5. ANECHOIC—Absent of sound

6. FIRSTINFIRSTOUT—Oldest requests receive priority [four words]

10. INTERFERENCE—The “I” in SQUID

11. CROSSTALK—Occurs when accidental coupling causes unwanted signals

12. BINISTOR—An electronic oscillator component

14. NANCY—Receiver that intercepts or demodulates IR radiation

16. BEAGLEA good breed of analyzer for I2C and SPI designs

 

Issue 284: EQ Answers

PROBLEM 1
Can you name all of the signals in the original 25-pin RS-232 connector?

ANSWER 1
Pins 9, 10, 11, 18, and 25 are unassigned/reserved. The rest are:

Pin Abbreviation Source Description
1 PG - Protective ground
2 TD DTE Transmitted data
3 RD DCE Received data
4 RTS DTE Request to send
5 CTS DCE Clear to send
6 DSR DCE Data Set Ready
7 SG - Signal ground
8 CD DCE Carrier detect
12 SCD DCE Secondary carrier detect
13 SCTS DCE Secondary clear to send
14 STD DTE Secondary transmitted data
15 TC DCE Transmitter clock
16 SRD DCE Secondary received data
17 RC DCE Receiver clock
19 SRTS DTE Secondary request to send
20 DTR DTE Data terminal ready
21 SQ DCE Signal quality
22 RI DCE Ring indicator
23 - DTE Data rate selector
24 ETC DTE External transmitter clock

 

PROBLEM 2
What is the key difference between a Moore state machine and a Mealy state machine?

ANSWER 2
The key difference between Moore and Mealy is that in a Moore state machine, the outputs depend only on the current state, while in a Mealy state machine, the outputs can also be affected directly by the inputs.

 

PROBLEM 3
What are some practical reasons you might choose one state machine over the other?

ANSWER 3
In practice, the difference between Moore and Mealy in most situations is not very important. However, when you’re trying to optimize the design in certain ways, it sometimes is.

Generally speaking, a Mealy machine can have fewer state variables than the corresponding Moore machine, which will save physical resources on a chip. This can be important in low-power designs.

On the other hand, a Moore machine will typically have shorter logic paths between flip-flops (total combinatorial gate delays), which will enable it to run at a higher clock speed than the corresponding Mealy machine.

 

PROBLEM 4
What is the key feature that distinguishes a DSP from any other general-purpose CPU?

ANSWER 4
Usually, the key distinguishing feature of a DSP when compared with a general-purpose CPU is that the DSP can execute certain signal-processing operations with few, if any, CPU cycles wasted on instructions that do not compute results.

One of the most basic operations in many key DSP algorithms is the MAC (multiply-accumulate) operation, which is the fundamental step used in matrix dot and cross products, FIR and IIR filters, and fast Fourier transforms (FFTs). A DSP will typically have a register and/or memory organization and a data path that enables it to do at least 64 MAC operations (and often many more) on unique data pairs in a row without any clocks wasted on loop overhead or data movement. General-purpose CPUs do not generally have enough registers to accomplish this without using additional instructions to move data between registers and memory.

Electrical Engineering Crossword (Issue 285)

The answers to Circuit Cellar’s April electronics engineering crossword puzzle are now available.

285-crossword-keyAcross

2.    STOKESSHIFT—Can reduce photon energy [two words]
8.    HYSTERESISLOOP—Its area measures the energy dispersed during a magnetization cycle [two words]
11.    NANDGATE—A shoe in when playing “true or false?” [two words]
13.    YOCTOPROJECT—An open-source alliance designed to help Linux aficionados [two words]
15.    RANKINE—°R
17.    INTERNALNET—A network that resides in and around you
18.    SEQUENTIALCIRCUIT—Dependent on past input [two words]
19.    NANOHENRY—Its abbreviation is the same as the state bordered by Massachusetts, Maine, and Vermont
20.    BINARYCODEDDECIMAL—Makes good use of a 4- or 8-bit nibble [three words]

Down

1.    BIREFRINGENCE—Divides light into ordinary and extraordinary rays
3.    SQUIRREL—An object-oriented programming language
4.    SMARTMETER—Records and shares energy usage information [two words]
5.    MESHANALYSIS—A circuit evaluation method [two words]
6.    LYOTFILTER—Uses [1. Down] to produce a narrow frequency range of wavelengths [two words]
7.    LINEARREGULATOR—Keeps things steady [two words]
9.    BRAGGDIFFRACTION—Occurs when electromagnetic radiation disperses [two words]
10.    AUTODYNE—An amplifying vacuum tube-based circuit
12.    FEMTOWATT—10–15 W
14.    UNIJUCTION—Can be used to measure magnetic flux
16.    PEAKER—Increases gain at higher frequencies