High-Performance Analog Technology A30 for IoT Applications and More

ams AG recently announced the availability of its High Performance Analog Low Noise CMOS process (“A30”). The new A30 technology features performance optimized, isolated 3.3-V devices (NMOSI and PMOSI), isolated 3.3-V low Vt devices (NMOSIL and PMOSIL), an isolated high-voltage device with thin gate oxide (NMOSI20T), vertical bipolar transistors (VERTN1 and VERTPH), and an isolated 3.3-V super-low-noise transistor (NMOSISLN). It enables flicker noise reduction by at least a factor of 4 to 10 for high drain currents compared to H35 process. Passive devices such as various capacitors (poly, sandwich, and MOS varactor) and resistors (diffusion, well based, poly, high resistive poly and precision) complete the device offering.

The A30 process is well suited for ultra-low noise sensing applications and analog read-out ICs that require noise optimized input stages or high signal-to-noise ratios. It allows the development of innovative solutions for consumer electronics, automotive, medical and IoT devices. The A30 process is fully qualified and manufactured in ams’ state of the art 200-mm fabrication facility ensuring very low defect densities and highest yield. All 0.30-µm elements are drawn and verified as 0.35µm devices. The optical shrink (factor of 0.9) is done in the mask shop on the completed GDSII data and results in smaller die sizes respectively more dies per wafer.

The A30 process is supported by the well-known hitkit, ams’s industry benchmark process design kit. Based on Virtuoso Custom IC technology 6.1.6 from Cadence, the new hitkit helps design teams to significantly reduce time-to-market for products in the analog-intensive, mixed-signal arena. The hitkit provides a comprehensive design environment and a proven route to silicon. The new hitkit v4.15 for A30 process is now available on ams’s foundry support server.

Source: ams

Registration to Attend the 2014 Design and Verification Conference

Registration to attend the 2014 Design and Verification Conference (DVCon) opens December 6, 2013. The conference will be held March 3-6, 2014, at the DoubleTree Hotel in San Jose, California.

DVCon is a premier conference for the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits, according to the website dvcon.org. DVCon primarily focuses on the practical use of specialized design and verification languages such as SystemC,  SystemVerilog and e, assertions in SVA or PSL, as well as the use of AMS languages, design automation using IP-XACT,  and the  use of general-purpose languages C and C++.

Conference attendees are generally designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools.  The 2013 conference drew a record turnout. Overall attendance rose to 883, including full conference and exhibit only registration.

If you are interested in attending the conference,  becoming a DVCon exhibitor, or obtaining more information about DVCon, please visit the conference website.  

DVCon is sponsored by Accellera Systems Initiative, an independent, nonprofit industry consortium dedicated to the development and standardization of design and verification languages. The organization accelerates standards development, and as part of its ongoing partnership with the Institute of Electrical and Electronics Engineers (IEEE), its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control.