SYSTEM TIMING ANALYSIS

To achieve CD-quality audio (16-bit stereo with a 44.1 kHz sampling frequency), the required bit rate is 1,411,200 Hz (i.e., 16 bits (resolution) × two channels (stereo) × 44.1 kHz (Fs)). For 48 kHz, the bit rate is 1,536,000 Hz. This is the clock generated by the synchronous serial port (SSP), supplying data continuously to an audio DAC.

With a 12-MHz crystal (as used on Olimex and Embedded Artists evaluation boards), the timing is very close. The system clock generated by PLL from a 12-MHz crystal is CCLK = 60 MHz.

The other possible crystals are 11.2896 and 12.288 MHz. For Philips LPC21xx microcontrollers, the clock of the SSP is derived from peripheral clock PCLK, which is PCLK = CCLK/VPB. Its maximum value can equal to CCLK (when the VPB divider is 1). There is another divider hold in the CSPCPSR register to define the clock of the SSP (SCK1).

Table 1 shows some combinations of crystals and settings. If you want to use another clock or sampling rate, you can easily calculate your settings.

The data has to be read from the file on an SD card. The card is in FAT format, and it’s compatible with a PC. The data has to be read and processed in real time. The processing required is very simple for uncompressed audio. It’s more complex for compressed audio like MP3, which requires complex decoding.