June 2005, Issue 179

Accurate Capacitance Meter
Cypress PSoC High Integration Challenge 2004 Contest Winner

POSSIBLE PITFALLS

When designing measurement equipment, it’s important to assert all known sources of error and design ways to eliminate or at least minimize them. It will be worth your time to plan ahead for possible problems.

This project involves extremely sensitive circuitry, so a component parameter gone astray can throw off the measurements. Fortunately, there are ways to account for the sources of system error. The current source, for example, may be rock steady but at the wrong value because of an incorrect value of the setting resistor. Thus, the introduced error will be linearly proportional to the deviation. You can compensate for it by adjusting the value of the current source resistor.

Another possible source of error is a nonlinear response of the current source within the required operational voltage range. If the current source isn’t up to the task, it will cause inaccuracies. To prevent this from happening, we designed our current source to operate well within a safe voltage range. We implemented the current source in the CY8C27443 after reading Dave Van Ess’s “AN2089: Programmable Bipolar Analog Current Source. PSoC Style.” Everything remained under the same roof as the rest of the device.

Some implementations of a current source are frequency dependent. With such circuits, charging the capacitor too quickly (fast slew rate) may lead to significant errors in the current supplied. Because we charge large capacitors with a low current, our device operates well outside this speed range and isn’t susceptible to this type of error. It’s possible that the DAC reacts differently to positive and negative settings. Because the DAC sets the current source operating voltage, such a difference would introduce an error. As a safety precaution, we measure both the charging and discharging time of C_X and average the two readings to obtain a final result.

This approach also significantly reduces errors caused by different hystereses in the comparators. However, in typical implementations, they also may be a source of error if their response times are different. In the PSoC, the comparators are implemented internally using equivalent PSoC blocks. They’re clocked by the same source and powered by the same supply. It’s safe to assume that their response times are equal so you can ignore this source of error.

The comparators’ input offset voltage also affects the total measuring error. To minimize the error, you can increase the threshold voltages as well as the difference between them. The larger the gap between the two values, the smaller the relative error. The higher the voltages, the smaller the absolute error. Be careful tweaking this parameter. The comparators’ threshold voltages must be set so they don’t affect the proper operation of the current source. In addition, a larger gap means larger measuring times. We fine-tuned this parameter to achieve relatively high responsiveness from the capacitance meter while still obtaining respectable accuracy. Finally, to minimize errors caused by a drift or instability in the frequency that clocks the timer, we used an external quartz crystal to generate the CY8C27443’s system clock.