June 2005, Issue 179

Precision Frequency Meter
Cypress PSoC High Integration Challenge 2004 Contest Winner

CLOCK COUNTER

The ClockCounter 16-bit timer counts system clocks from the reference oscillator. Always operating, it never resets. At overflow (approximately every 4 ms), an ISR increments a software counter to provide 32 more high bits for the counter. The combined hardware/software counter is therefore 48 bits (2.8 × 1014). At 16.3676 MHz, this counter would take 199 days to roll over.

The ClockCounter includes a capture input and register that can be activated from either the audio comparator outputs (as a result of the edge of an audio pulse) or the input signal divider (because of a number of input signal cycles). A capture also causes a software interrupt that records the captured counter value along with the software counter bits and the counter overflow interrupt register. The latter is recorded to enable a software correction of the counter value. Correcting the counter high bits is necessary if a counter overflow occurs close to a capture event. The capture sources have a higher priority, so data will be recorded before the counter high bits have been incremented. After software corrections are applied, the software can get the exact clock count at the event. The two capture sources are selected by directly manipulating the ClockCounter input multiplexer register.