DDS Basics (EE Tip #122)

The simplest form of a digital waveform synthesizer is a table look-up generator (see Figure 1). Just program a period of the desired waveform in a digital memory (Why not an EPROM for old timers?), connect a binary counter to the address lines of the memory, connect a DAC to the memory data lines, keep the memory in Read mode, clock the counter with a fixed-frequency oscillator FCLOCK, and voilà, you’ve got a waveform on the DAC output. Don’t forget to add a low-pass filter to clean the output signal, with, as you know, a cut-off frequency a little less than FCLOCK/2 to please Mr. Nyquist.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

This design works, but it is not too flexible. If you want to change the output frequency, you need to change the clock frequency, which is not easy to do, especially if you need a fine resolution.

The direct digital synthesizer (DDS) architecture is an improvement on this original design (see Figure 2). Rather than add one to the table look-up address counter at each clock pulse like the counter did in the previous example, a DDS uses an N-bit long-phase register and adds a fixed-phase increment (W) at each clock pulse to this register.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

N can be quite high (e.g., 32 or 48 bits), so only the most significant bits of the phase register are used to select a value from the phase-to-amplitude look-up table, which is usually nothing more than a ROM preprogrammed with a sine waveform. Assume that you are using the P most significant bits as an address. Then the output of the lookup table is routed to a DAC. And, of course, the analog signal finally goes through a low-pass filter, which is called a “reconstruction filter.” You will understand why in a minute.

How does it work? If the phase increment W is set to one, you will need 2N clock pulses to go through all of the values of the look-up table. One sine period will be generated on the FOUT output each 2N clock pulses, exactly like the aforementioned counter-based architecture. If W is 2, it will be twice as fast and the output frequency will be doubled. As you know, you need a little more than two samples per period to be able to reconstruct a sine signal, so the maximum value of W is 2N–1 – 1. The formula giving the output frequency based on the phase increment is then:DDS-EEtip-122-eq1

Don’t be confused. It is not a simple programmable divider because the phase register doesn’t loop back to the same value after each generated period. The table in Figure 3 may help you understand it.

Figure 3: his spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

Figure 3: This spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

What make a DDS a fantastic building block are the numeric examples. Just take a standard, low-performance DDS with a phase register of N = 32 bits and a reference clock FCLOCK = 20 MHz. Your DDS can then generate any frequency from DC to nearly 10 MHz with a resolution of the following:DDS-EEtip-122-eq2

Not bad. In fact, the maximum frequency will be a little lower due to constraints on the low-pass filter.—Robert Lacoste, “Direct Digital Synthesis 101,” Circuit Cellar 217, 2008. The issue is available in the CC Webshop.

 

One thought on “DDS Basics (EE Tip #122)

  1. This is always a tough unit in my Embedded Systems class. I recall that Robert had a nice article on anti-alias filters – this would make a nice EE tip, and quiz for my students :)