Here are the answers to the four EQ problems that appeared in Circuit Cellar 322. Problem 1: Some time ago (Issue #274), we discussed how theoretical channel capacity is a function of the bandwidth and the signal-to-noise ratio of the … Continue reading

__# Category Archives: Test Your EQ (Engineering Quotient)

Problem 1: A certain CPU has three blocks of combinatorial logic that are used in each instrucion cycle, and these have delays of 7 ns, 3 ns, and 10 ns, respectively. A register in this technology has a total of 2 ns of setup … Continue reading

__Here are the answers to the four EQ problems that appeared in Circuit Cellar 318. Problem 1: Outside of simply moving data from one place to another, most of the work of a computer is performed by “dyadic” operators — … Continue reading

__Question 1: What is the second grid in a tetrode vacuum tube for? How about the third grid in a pentode? Answer 1: In a triode, there is a certain amount of capacitance between the control grid and the plate, which contributes … Continue reading

__Answer 1—Intersymbol interference is created by nonlinearities in the phase/frequency response of the RF channel. These irregularities are generally proportional to the carrier frequency — for example, if a channel centered at 1 MHz has a quality factor (Q) of … Continue reading

__Question 1: What is the probably of a flip-flop with a uniformly-distributed asynchronous input going metastable? Answer 1: The probably that a flip-flop with a uniformly-distributed asynchronous input will go metastable is a function of how wide its “window of opportunity” (the … Continue reading

__Answer 1: UDP packets are subject to the following problems. Packets may be lost. Packets may experience variable delays. Packets may arrive in a different order from the order they were transmitted. UDP gives the application the ability to detect and deal with … Continue reading

__Problem 1—The circuit shown below is an audio amplifier with a slightly unusual topology. Explain how to analyze its DC operating point. Answer 1—For the DC analysis, start by calculating the Thevenin equivalent of the bias network: 8.0 V and 16.67 kΩ. … Continue reading

__Problem 1—The following circuit was designed to be an inrush current limiter for the large (40,000 µF) capaitor C1. R7 represents the application load of about 180 mA at 9 V. The load on the 9-V source (Vin) needed to … Continue reading

__Problem 1: You have decided to build a small computer from discrete transistors as a demonstration. After researching the available technologies, you have decided to base your design on NMOS logic, using a 3-input NOR gate as your basic building block, … Continue reading

__Problem 1: The diagram below is a simplified illustration of a switchmode “buck” DC-DC converter with synchronous (active) rectification. The switching elements are shown as MOSFETs, with the associated body diodes drawn explicitly. The details associated with driving the MOSFET gates … Continue reading

__Problem 1: What do we call a network of gates that has no feedback of any kind? What is its key characteristic? Answer 1: A network of gates that has no feedback is called “combinatorial logic”, or sometimes “combinational logic”. Its defining characteristic … Continue reading

__Answer 1—The frequency generated at the QB output of the counter is 16.000 MHz × 3 / 13 = 3.6923 MHz. The ratio between this and 3.6864 MHz is 1.0016, so the error expressed as a percentage is +0.16%. This is well within … Continue reading

__Problem 1—Let’s get back to basics and talk about the operation of a capacitor. Suppose you have two large, flat plates that are close to each other (with respect to their diameter). If you charge them up to a given … Continue reading

__Problem 1—Let’s talk about noise! There are different types of noise that might be present in a system, and it’s important to understand how to deal with them. For example, analog sensors and other types of active devices will often … Continue reading

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