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Telit Announces IoT Innovation Conference

Telit announced that it will soon open registration for the 2016 Telit IoT Innovation Conference, which will take place on Tuesday, September 6, 2016 at Caesars Palace in Las Vegas. The one-day, multi-track conference will feature business use cases and provide you with tools for building your network and enabling connected devices.

As an attendee, you can study real IoT business use cases, network with IoT innovators, discover new technologies for IoT solution deployment, connect with partners, and learn more about Telit products and its IoT ecosystem.

Registration opens soon!

Source: Telit

embOS-MPU Brings Security to Embedded Systems

SEGGER recently launched the embOS-MPU, which is a new variant of its zero interrupt latency real-time operating system (RTOS) that is optimized for minimal memory utilization. Using the microcontroller’s memory protection unit (MPU) or memory management unit (MMU) capabilities, it can protect a system from the potential harm posed by errant threads.SEGGER HRES

With embOS-MPU, a particular task failure won’t impact the entire system. Using it, you can develop an unlimited number of privileged and unprivileged tasks. The latter receive a set of restricted rights (e.g., memory write access). When an unprivileged task attempts to violate predefined limits or causes a system error (e.g., stack overflow), the task is immediately terminated.

With the embOS-MPU can also install a callback function that is activated if an unprivileged task is terminated. This application-defined routine can take whatever action is necessary when this exceptional condition is triggered. It could log the problem and recover to restore full functionality, degrade system performance, or shut down the entire system in a failsafe manner.

Source: SEGGER Microcontroller

Minimum Mass Waveform Capture

I can capture repetitive waveforms at 1 Msps using a microcontroller’s on-chip PWM and comparator. The impetus for developing this technique came from my own need to capture repetitive waveforms using the least expensive and lowest part count means possible. I wanted to be able to view the waveforms on an LCD dedicated to the purpose or upload the waveform to a computer for manipulation on a spread­sheet. This waveform capture method adheres to the “minimum mass” product design concept: it doesn’t use anything that is not absolutely essential to obtaining the needed function.

Implementations can be cheap enough to allow capture and analysis in many applications that otherwise could not justify the cost. Such applications include calculating the RMS values or harmonic content of waveforms for power management and equipment maintenance, self-testing audio frequency circuits, the analysis of pulse response for self-tuning servos, signal signature analysis, and remote diagnostics and data gathering.

The approaches using on-chip A/D converters on AVR and PIC controllers reach sample rates of up to nearly 60 kHz. Exotic and pricey high-speed controllers top out around 100 kHz. Such a sampling rate is not really high enough for the sort of applications I had in mind: encoded data, radio control signals, A/D converter waveforms, checking the dynamic range of amplifiers and capturing audio frequency waveforms for filtering, and power calculations. I realized that the comparators in AVR and PIC devices have fast response times (several hundred nanoseconds) and that the pulse width modulation (PWM) circuit could be made fairly responsive. I just needed some way to quickly combine them to sample analog values.

Eventually it became apparent that repetitive sampling was the only way to get high enough voltage and temporal sampling resolution using only these on-chip components. Rather than trying to sample and digitize the waveform in real time as it comes in, this method finds out a little bit about the waveform using the relatively high-speed comparator every time the waveform is repeated; it builds a more detailed picture with each repetition by changing the relatively low-speed PWM voltage each time.

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THE METHOD

To capture a waveform, the PWM D/A converter (PWM DAC) is set to its maximum output voltage. Then, using timing loops to generate regularly spaced sampling times (1 µs in Figure 1), the microcontroller looks at the output of the voltage comparator to determine if the incoming voltage is higher than the PWM voltage. At each sampling time, if the PWM voltage is at a higher voltage than that of the incoming waveform, the PWM value is stored in a RAM array location corresponding to that sampling time.

Figure 1—It’s all in the timing. Firmware timing loops set the interval between samples in a burst of waveform samplings that starts with a trigger signal. The green dots represent voltage levels of the sampled signal at the time of sampling.

Figure 1—It’s all in the timing. Firmware timing loops set the interval between samples in a burst of waveform samplings that starts with a trigger signal. The green dots represent voltage levels of the sampled signal at the time of sampling.

After all of the sample times have been tested against the PWM voltage, the PWM voltage is decremented. The process is then repeated until the PWM voltage has been reduced to its mini­mum value (0 V). Each scan of the sample time starts by a trigger signal that’s derived from, or in some way related to, the incoming waveform. The finer the voltage resolution, the longer it takes to capture the wave­form because the waveform has to be sampled more times. Note that the settling time for the PWM DAC needs to be longer for finer voltage resolution.

The total capture time (TCAP) equals: the number of voltage levels × (trigger latency + sample time + step settling time). Trigger latency is the average amount of time the controller waits for a trigger signal. The initial PWM settling time and the step settling time are the times for the PWM filter to charge to its initial value and settle after a 1-LSB step change, respectively. Capturing 100 samples at 1 Msps in a circuit optimized for 6-bit resolution (64 levels) takes approximately 69 ms; however, it takes about 1.3 s to measure the same waveform on a circuit optimized for 8-bit resolution.

When capturing waveforms with long periods, the total time needed to capture the waveform is dominated by the time it takes the waveform to make the requisite number of repetitions. For shorter periods, the total time is dominated by the settling times for the PWM. Thus, the higher the sampling rate, the more you can speed up the capture cycle by using a faster DAC. A resistor network connected to some port pins could suffice for low-resolution (6-bit) waveform capture. An integrated circuit DAC would be better for higher resolution applications.

The quality of the trigger signal is essential to the fidelity of the captured waveform. The trigger signal must consistently appear at the same time with respect to the captured signal, otherwise severe distortion will result. This means that a noisy trigger signal, such as one derived directly from a noisy input signal, would give poor results. You’ll get the best results with a digital trigger signal taken directly from the source of the signal if such a trigger source is available.

Unsynchronized signals (e.g., noise) are not represented accurately; instead, such signals are underrepresented in the captured waveform. This quality, which results from synchronous sampling, is sometimes a good thing because it can effectively pull a signal out of the noise, which is an important property in applications such as ultra wideband and spread-spectrum signal decoding. But, if you intend to measure noise or jitter, this quality makes the system inappropriate.

Another aspect of sampled data sys­tems is their susceptibility to aliasing. Aliasing is a phenomenon in which a signal appears to occur at a frequency other than that at which it actually occurs. For instance, when a 250-kHz square wave is viewed with a 1-µs sampling interval, it shows up properly as four samples per cycle; however, when it is captured at a 100-µs sampling interval, it appears as 16 samples per cycle, or a 625-Hz signal, which is one four-hundredth the actual frequency.

To prevent aliasing, insert an analog filter in the signal path before the comparator’s input. In the example I’ve been focusing on, the Atmel AT90S2313 samples the signal at 1 Msps. The on-chip comparator has a propagation delay of 500 to 700 ns, providing inherent filtering for components of signals above approximately 800 kHz, and thus restricting the range of frequencies above the sam­pling rate that can be aliased down to frequencies below the sampling rate. To reduce the aliasing of signal components that have a lower frequency than the sampling rate, you’d need an additional external analog filter.

Figure 2— You can work with a bare minimum of parts, because it doesn’t take much to capture repetitive waveforms at 1 Msps and upload them to a terminal program on a PC for display and analysis. The passive components connected to pins 13 and 15 of the microcontroller are in the same basic configuration used for successive approximation A/D conversion; only the firmware is different.

Figure 2—You can work with a bare minimum of parts, because it doesn’t take much to capture repetitive waveforms at 1 Msps and upload them to a terminal program on a PC for display and analysis. The passive components connected to pins 13 and 15 of the microcontroller are in the same basic configuration used for successive approximation A/D conversion; only the firmware is different.

AN IMPLEMENTATION

The simple implementation shown in Figure 2 needs only a microcontroller with a DAC and voltage comparator, and some way to get control signals into the chip and the data back out. The demonstration system, for which firmware is posted on the Circuit Cellar ftp site, assumes an Atmel AT90S2313­10 is connected to level-shifting invert­ers for the EIA-232 interface such as a Maxim MAX232 with its 1-µf capaci­tors, a 10-MHz crystal with load capacitors, a decoupling capacitor, and the PWM low-pass filter connected to pins 13 and 15 of the microcontroller (see Photo 1).

Photo 1—The only components added to the operating Atmel AT90S2313 circuit needed to allow for waveform sampling with less than 1-μs resolution at 1-V full scale are the capacitor and two resistors. Imagine how small the circuit will be using surface-mount components.

Photo 1—The only components added to the operating Atmel AT90S2313 circuit needed to allow for waveform sampling with less than 1-μs resolution at 1-V full scale are the capacitor and two resistors. Imagine how small the circuit will be using surface-mount components.

It can be controlled by and dump data to an ASCII terminal program such as HyperTerminal at capture rates from 1 µs per sample to 10 ms per sample at 6-, 7-, and 8-bit resolution with selectable trigger polarity. An example of a waveform captured with this system and plot­ted in a spreadsheet program is shown in Figure 3.

Figure 3—This is the capture of a 31.25-kHz sawtooth waveform. The sample rate is set to 1 μs per sample and the voltage resolution is 8 bits.

Figure 3—This is the capture of a 31.25-kHz sawtooth waveform. The sample rate is set to 1 μs per sample and the voltage resolution is 8 bits.

PWM LOW-PASS FILTER

The DAC uses pulse-width modula­tion, so it is necessary to have an averaging (low-pass) filter to recover the DC component while filtering out most of the PWM signal’s AC component. The AC component remaining on the filter’s output is referred to as ripple.

The filter is made up of 330- and 82-kΩ resistors and a 0.047-µF capaci­tor, which forms a single-pole RC fil­ter. The two resistors form a voltage divider to reduce the full-scale voltage from the DAC to 1-V full scale. If you are worried about accuracy, you can replace the 82-kΩ resistor with a fixed resistor and a variable resistor in series to allow for full-scale calibration.

If 5-V full scale is appropriate for your application, you can omit the lower resistor and save a part. The low-pass filter for the PWM output needs to be made with a large enough time constant to keep the ripple to an acceptable level. After the filter time constant is pinned down, the controller must wait long enough after each step change in output voltage for the filter to settle adequately before starting measurements.

The PWM filter can be analyzed as a single resistor driving the capacitor (see Figure 4). Judging from the AT90S2313 datasheet, when operating at 5 V, the output resistance of the PWM output is approximately 28 Ω; it is safe to say that it is negligible com­pared to the 330-kΩ resistor that’s in series with it. Thus, the filter model is plenty close by taking the value of the resistance to be the parallel combina­tion of the two resistors (see Figure 4).

Figure 4—The PWM filter is easily analyzed as a single resistor charging the capacitor by replacing the resistors with a single resistor equal to the parallel combination of the two, because that is what it looks like to the capacitor.

Figure 4—The PWM filter is easily analyzed as a single resistor charging the capacitor by replacing the resistors with a single resistor equal to the parallel combination of the two, because that is what it looks like to the capacitor.

The first step is to select the time constant that gives an acceptably low ripple. For my application, I considered speed to be more important than absolute accuracy, so I decided to keep the ripple at 1 LSB. The time constant should be figured for the worst possible PWM signal. The worst case for ripple is when the lowest frequency appears at the filter’s input. In the case of the AT90S2313, this occurs when the PWM output runs 50% duty cycle. Under this condition, the pulse frequency is about 19.6 kHz and the voltage across the capacitor is 0.5 V. When the pulse is high (this analysis is the same for the time the pulse is low, only the signs change), the difference between the PWM peak voltage (1 V) and the voltage across the capacitor is across the equivalent resistance, and the current through the resistance charges the capacitor.

Note that 1 LSB of an 8-bit value based on 1-V full scale is 4 mV (1/255). Using the formula in Figure 5, the time constant must be approximately 3.2 ms. I chose the resistors by first selecting the largest capacitor and a pair of large resistors that had the necessary 4:1 resistance ratio while simultaneously giving nearly the correct time constant. The resulting combination gives a divide ratio of 1:5.02 and a time con­stant of 3.15 ms (67 kΩ × 0.047 µF).

Figure 5—A simplified model can be used to predict the relationship between the filter’s time constant and the amount of ripple. The charging current for the capacitor comes from the voltage drop between the 1 V from the output of the resistive divider and the voltage across the capacitor. Note that EO is the voltage change across the capacitor (1 LSB = 4 mV), and EI is the average voltage across the resistance (0.5 V). T is the time that voltage is applied across the circuit (25.5 μs), and t is the time constant of the circuit.

Figure 5—A simplified model can be used to predict the relationship between the filter’s time constant and the amount of ripple. The charging current for the capacitor comes from the voltage drop between the 1 V from the output of the resistive divider and the voltage across the capacitor. Note that EO is the voltage change across the capacitor (1 LSB = 4 mV), and EI is the average voltage across the resistance (0.5 V). T is the time that voltage is applied across the circuit (25.5 μs), and t is the time constant of the circuit.

After the filter time constant is known, the settling times can be determined. I decided to have the con­troller wait for the initial settling of the filter to within 1 LSB of full scale before starting the waveform capture cycle using the formula in Figure 6. For the settling time between succes­sive steps, I wanted to wait until after the voltage changed more than 0.5 LSB. Because the step size is 1 LSB, I chose one time constant, or 3 ms.

Figure 6—The initial settling time must be long enough to assure that the PWM output settles to within 1 LSB of the final voltage. It must be calculated for the worst case scenario, which is when it starts from 0 V. Note that ΔV is the error in the settled voltage (1 LSB = 4 mV). EI is the voltage applied to the circuit, which is 1 V. In is the natural logarithm (base 2.71828…). T is the time that voltage is applied across the circuit, and t is the time constant of the circuit (3.17 ms).

Figure 6—The initial settling time must be long enough to assure that the PWM output settles to within 1 LSB of the final voltage. It must be calculated for the worst case scenario, which is when it starts from 0 V. Note that ΔV is the error in the settled voltage (1 LSB = 4 mV). EI is the voltage applied to the circuit, which is 1 V. In is the natural logarithm (base 2.71828…). T is the time that voltage is applied across the circuit, and t is the time constant of the circuit (3.17 ms).

FIRMWARE

When capturing a waveform, the PWM circuit first generates the maxi­mum output voltage and samples all time intervals starting from a trigger signal, taking care to keep the time between samples constant. Whenever the voltage at a sampled time exceeds the PWM voltage, the PWM value is stored in the RAM array location corresponding to that sample. In this way, at the end of the capture cycle, the peak value at each sampling time is stored in the RAM array.

The sampling loop in Listing 1 is the time-critical part of the code. It requires 10 clock cycles per sample. With a 10­-MHz clock, the sampling rate is 1 MHz. Two clock cycles are taken up by the indirect jump instruction (ijmp), which jumps either to the next instruction in sequence (at the label oneus:) or to a delay routine that returns to the next instruction in sequence. Eliminating the indirect jump instruction would decrease the sampling interval to eight cycles. Straight line coding would be inflexible and take a lot of program memory, but it could reduce the sam­pling interval to as few as three cycles when storing the waveform in RAM.

Listing 1—The sampling of the waveform takes place at the sbic ACSR,5 instruction, where the output of the comparator is tested. If the comparator’s output is low, execution proceeds to st Y+,pwmval, the instruction that stores the data into the RAM array via the Y pointer. If the comparator’s input is high, the program branches back to nextydelay, which imcrements the Y pointer without storing data.

Listing 1—The sampling of the waveform takes place at the sbic ACSR,5 instruction, where the output of the comparator is tested. If the comparator’s output is low, execution proceeds to st Y+,pwmval, the instruction that stores the data into the RAM array via the Y pointer. If the comparator’s input is high, the program branches back to nextydelay, which imcrements the Y pointer without storing data.

At the beginning of a waveform collection cycle, the program sits in a wait loop and waits for a transition on the trigger input. After the triggering edge is detected, the sampling routine is called and it runs through and collects a full set of samples. Then, the PWM value is decremented, a wait loop is executed to allow the RC filter in the PWM DAC to settle, and the program returns to wait for the next triggering event. This process continues until the lowest pos­sible PWM value has been tested.

Timing uncertainty is introduced by the short loop in which the controller waits for the triggering edge. The uncertainty translates into jitter in the signal sampling. As long as the uncer­tainty is small compared to the signal-sampling interval, it should not contribute much in the way of noise to the captured waveform. In applications that use only a few machine cycles between samples, it pays to keep the wait loops as short as possible.

BELOW GROUND SIGNALS

Judging from the offset-versus-input voltage curve on the AT90S2313’s datasheet, the comparator’s differen­tial gain is good enough for 6-bit waveform capture just above ground. For linearity errors of less than 1 LSB with 8-bit operation, the comparator inputs need to run closer to the mid­dle of the power supply where the curve is nearly flat.

There is a bonus to adding offset to the input signal in that it can measure input signals at and below ground without clipping. When the input signal is level-shifted, the PWM DAC’s output must be similarly offset. The PWM offset circuit provides an oppor­tunity for an adjustable vertical-cen­tering control (to use the oscilloscope term). Circuits that shift the input level and allow offset adjustment are shown in Figure 7.

Figure 7—The FET provides an offset allowing the input to swing above and below ground as well as moving the input to the AT90S2313’s on-chip comparator away from ground and enabling an offset adjustment. You can also achieve these functions with op-amps, but there are several trade-offs to consider.

Figure 7—The FET provides an offset allowing the input to swing above and below ground as well as moving the input to the AT90S2313’s on-chip comparator away from ground and enabling an offset adjustment. You can also achieve these functions with op-amps, but there are several trade-offs to consider.

Level shifting is achieved easily enough with an op-amp if you have a negative power supply, but my objec­tive was to make the entire system operate from a single 5-V regulator. Besides, my cheap single-supply op-amps, which also had adequate dynam­ic range, had too poor a slew rate to give satisfactory performance at 1 Msps.
A junction field effect transistor (JFET) source follower is an ideal way to offset the input signal to a more positive voltage without much attenu­ation or loss of bandwidth. I used an MPF102 in my own circuit because I had some on hand. Numerous other small signal JFETs would work well.

Pinch-off voltage is the FET parameter that most affects the offset because, for most FETs, this parameter varies widely. To obtain the approximate 2.5-V offset (the DC voltage on the FET source when the gate is grounded), you can hand select an FET, adjust the source resistor (15 kΩ in the circuit above), or try a combination of the two. The higher the value of the resistor, the higher the off­set voltage (i.e., up to nearly the pinch-off voltage of the FET, which is usually specified at a low current). Be aware that the source resistor affects the trade-off between the bandwidth and signal loss. As the resistor gets larger, the bandwidth will decrease; as the resistor gets smaller, the gain of the source follower drops. For my particular circuit layout and its parasitic capacitance, 15 kΩ was about the upper limit for 1 Msps.

One way to add an adjustable DC offset to the output of the PWM circuit without affecting the RC filter’s response time is to use an adjustable constant current source. The current source shown in Figure 7 relies on the fact that the 2N2907’s collector current is nearly equal to the emitter current. (The collector cur­rent equals the emitter current times Alpha, which is nearly unity and pretty stable.) Emitter current is determined by the voltage across the 8.2-kΩ emitter resistor, which follows the base voltage and is temperature-compensated by the diode in series with the potentiometer.

SIMPLE, ECONOMICAL, FLEXIBLE

Among the variations that may be useful are programmable offset and gain controls, and a calibration func­tion using only a few resistors and additional I/O pins. In multiple-chip systems, the time-dependent sampling task can be offloaded to a low-cost slave processor with little or no RAM that sends intermediate results to a host. The slave could be one of the cheapest eight-pin microcontrollers offered that has a suitable on-chip voltage comparator. The minimum mass waveform capture approach is a building block that produces a much faster sampling rate and costs less than conventional approaches using on-chip A/D converters.

I suspect that by now you have come up with some ideas of your own. It’s easy enough to put the sam­ple system together, so why not give it a try?

ABOUT THE AUTHOR

Dick Cappels enjoys tinkering with and writing about analog circuits and microcontrollers. He has published several papers relating to electronic displays in computer systems, and is currently active in the Society for Information Display. Dick holds 17 U.S. patents.

This article first appeared in Circuit Cellar 159.

May Engineering Challenge: Find the Schematic Error

Challenge 2 for web

The May Electrical Engineering Challenge (sponsored by Technologic Systems) is now live! Review the schematic on the challenge webpage and find the error for a chance to win prizes, such as a TS-7250-V2 High-Performance Embedded Computer or a Circuit Cellar Digital Subscription.

Circuit Cellar’s technical editors purposely inserted an error in the schematic diagram. It could be a design error, symbol-related error, value error (e.g., 10k vs 100k), incorrect part usage, or some other problem that negatively affects the electronics. Find the error and submit your answer via the online form by the deadline (2 PM EST on the 20th of the month).

TS7250-V2

TS7250-V2

Circuit Cellar will randomly select winners from the pool of respondents who submit the correct answer. For more information, read the Rules, Terms, & Conditions.

The Future of Electronic Measurement Systems

Trends in test and measurement systems follow broader technological trends. A measurement device’s fundamental purpose is to translate a measurable quantity into something that can be discerned by a human.  As such, the display technology of the day informed much of the design and performance limitations of early electronic measurement systems. Analog meters, cathode ray tubes, and paper strip recorder systems dominated.  Measurement hardware could be incredibly innovative, but such equipment could only be as good as its ability to display the measurement result to the user. Early analog multimeters could only be as accurate as a person’s ability to read to which dash mark the needle pointed.ipad_hand

In the early days, the broader electronics market was still in its infancy and didn’t offer much from which to draw. Test equipment manufacturers developed almost everything in house, including display technology. In its heyday, Tektronix even manufactured its own cathode ray tubes. As the nascent electronics market matured, measurement equipment evolved to leverage the advances being made. Display technology stopped being such an integral piece. No longer shackled with the burden of developing everything in house, equipment makers were able to develop instruments faster and focus more on the measurement elements alone. Advances in digital electronics made digital oscilloscopes practical. Faster and cheaper processors and larger memories (and faster ADCs to fill them) then led to digital oscilloscopes dominating the market. Soon, test equipment was influenced by the rise of the PC and even began running consumer-grade operating systems.

Measurement systems of the future will continue to follow this trend and adopt advances made by the broader tech sector. Of course, measurement specs will continue to improve, driven by newly invented technologies and semiconductor process improvements. But, other trends will be just as important. As new generations raised on Apple and Android smartphones start their engineering careers, the industry will give them the latest advances in user interfaces that they have come to expect. We are already seeing test equipment start to adopt touchscreen technologies. This trend will continue as more focus is put on interface design. The latest technologies talked about today, such as haptic feedback, will appear in the instruments of tomorrow. These UI improvements will help engineers better extract the data they need.

As chip integration follows its ever steady course, bench-top equipment will get smaller. Portable measurement equipment will get lighter and last longer as they leverage low-power mobile chipsets and new battery technologies. And the lines between portable and bench-top equipment will be blurred just as laptops have replaced desktops over the last decade. As equipment makers chase higher margins, they will increasingly focus on software to help interpret measurement data. One can imagine a subscription service to a cloud-based platform that provides better insights from the instrument on the bench.

At Aeroscope Labs (www.aeroscope.io), a company I cofounded, we are taking advantage of many broader trends in the electronics market. Our Aeroscope oscilloscope probe is a battery-powered device in a pen-sized form factor that wirelessly syncs to a tablet or phone. It simply could not exist without the amazing advances in the tech sector of the past 10 years. Because of the rise of the Internet of Things (IoT), we have access to many great radio systems on a chip (SoCs) along with corresponding software stacks and drivers. We don’t have to develop a radio from scratch like one would have to do 20 years ago. The ubiquity of smart phones and tablets means that we don’t have to design and build our own display hardware or system software. Likewise, the popularity of portable electronics has pushed the cost of lithium polymer batteries way down. Without these new batteries, the battery life would be mere minutes instead of the multiple hours that we are able to achieve.

Just as with my company, other new companies along with the major players will continue to leverage these broader trends to create exciting new instruments. I’m excited to see what is in store.

Jonathan Ward is cofounder of Aeroscope Labs (www.aeroscope.io), based in Boulder, CO. Aeroscope Labs is developing the world’s first wireless oscilloscope probe. Jonathan has always had a passion for measurement tools and equipment. He started his career at Agilent Technologies (now Keysight) designing high-performance spectrum analyzers. Most recently, Jonathan developed high-volume consumer electronics and portable chemical analysis equipment in the San Francisco Bay Area. In addition to his decade of industry experience, he holds an MS in Electrical Engineering from Columbia University and a BSEE from Case Western Reserve University.

Integrated High-Voltage GaN FET and Driver Solution

Texas Instruments recently announced the availability of 600-V gallium nitride (GaN) 70-mΩ field-effect transistor (FET) power-stage engineering samples. The 12-A LMG3410 power stage coupled with TI’s analog and digital power-conversion controllers enables you to create smaller, higher-performing designs compared to silicon FET-based solutions. These benefits are especially important in isolated high-voltage industrial, telecom, enterprise computing, and renewable energy applications.TI LMG3410

The LMG3410’s features and specifications:

  • Integrated driver and zero reverse-recovery current
  • Integrates built-in intelligence for temperature, current, and undervoltage lockout (UVLO) fault protection
  • Includes GaN FETs
  • Double the power density
  • Reduced packaging parasitic inductance
  • Enables new topologies

To support designers who are taking advantage of GaN technology in their power designs, TI also launched new products to expand its GaN ecosystem. The LMG5200POLEVM-10, a 48-V to 1-V point-of-load (POL) evaluation module, will include the new TPS53632G GaN FET controller, paired with the 80-V LMG5200 GaN FET power stage. The solution allows for efficiency as high as 92% in industrial, telecom, and datacom applications.

 

TI will offer a development kit that includes a half-bridge daughtercard and four LMG3410 IC samples. A second kit will include a system-level evaluation motherboard. When used together, the two kits enable immediate bench testing and design. The two development kits are available for $299 and $199, respectively.

Source: Texas Instruments

IAR Embedded Workbench Integrates the NXP S32 Design Studio

IAR Systems recently announced that IAR Embedded Workbench for ARM is now integrated with the NXP Semiconductors S32 Design Studio, which is an integrated development environment (IDE) for NXP’s automotive and ultra-reliable microcontrollers. In addition to functionality such as pin configurator, bootloader and motor control toolbox, it provides AUTOSAR Microcontroller Abstraction Layer (MCAL) support and AUTOSAR OS for the S32K product line tailored for automotive applications.

By letting S32 Design Studio generate a project connection with IAR Embedded Workbench, the IAR C/C++ Compiler and the extensive C-SPY Debugger can be used to develop the application. Adding a project connection will automatically include the generated code to the IAR Embedded Workbench project. If the files are changed from S32 Design Studio, they are updated automatically in IAR Embedded Workbench. Due to an integration of the build chain of IAR Embedded Workbench into the Eclipse-based S32 Design Studio, you can also opt to continue development within the S32 Design Studio while utilizing the IAR C/C++ Compiler.

The C/C++ compiler and debugger toolchain IAR Embedded Workbench for ARM features comprehensive debugging possibilities and smart integrated profiling tools. It is available with build chain certification according to the automotive functional safety standard ISO 26262. In addition, IAR Systems offers fully integrated static and runtime analysis tools for complete code control.

Source: IAR Systems

1.5-A Synchronous Step-Down DC/DC Converter Delivers 93% Efficiency

Linear Technology’s new LT8608 is a 1.5-A, 42-V input synchronous step-down switching regulator that delivers 93% efficiency while switching at 2 MHz. It is well suited for avoiding critical noise-sensitive frequency bands (e.g., AM radio) while using a compact footprint. Burst Mode operation keeps quiescent current under 2.5 µA in no-load standby conditions. Its 3-to-42-V input voltage range makes it ideal for automotive applications that must regulate through cold-crank and stop-start scenarios with minimum input voltages as low as 3 V and load dump transients in excess of 40 V. Its internal 2-A switches can deliver up to 1.5 A of continuous output current.Linear 8608

The LT8608 maintains a minimum dropout voltage of only 200 mV (at 500 mA) under all conditions. Spread-spectrum frequency modulation and special design techniques offer low EMI operation. In addition, a fast minimum on-time of only 45 ns enables 2-MHz constant frequency switching from a 16-V input to a 1.5-V output. The LT8608’s 10-lead thermally enhanced MSOP package and high switching frequency keeps external inductors and capacitors small for a thermally efficient footprint.

The LT8608’s features and specifications include:

  • Wide input voltage range: 3 to 42 V
  • Ultralow Quiescent Current Burst Mode operation:
    • Less 2.5-µA IQ Regulating 12 VIN to 3.3 VOUT
    • Output Ripple less than 10 mVPP
  • High Efficiency 2-MHz Synchronous Operation:
    • 93% Efficiency at 0.5 A, 5 VOUT from 12 VIN
  • 1.5-A Maximum Continuous Output Current
  • Fast Minimum Switch-On Time: 45 ns
  • Adjustable and Synchronizable: 200 kHz to 2.2 MHz
  • Spread-Spectrum Frequency Modulation for Low EMI
  • Allows Use of Small Inductors
  • Low Dropout
  • Peak Current Mode Operation
  • Accurate 1-V Enable Pin Threshold
  • Internal Compensation
  • Output Soft-Start and Tracking
  • Small 10-Lead MSOP Package

Source: Linear Technology

IAR Systems Supports Wireless Gecko SoCs for IoT connectivity

IAR Systems now supports Silicon Labs Wireless Gecko SoCs, which provide scalable solutions and include Thread and ZigBee stacks for mesh networks, intuitive radio interface software for proprietary protocols, and Bluetooth Low Energy technology for point-to-point connectivity. The IAR Embedded Workbench development provides extensive debugging and profiling possibilities such as complex code and data breakpoints, run-time stack analysis, call stack visualization, code coverage analysis, and integrated monitoring of power consumption. IAR Systems also offers integrated add-on tools for static analysis and run-time analysis.

Support for the Wireless Gecko SoCs is available using IAR Embedded Workbench for ARM, from version 7.60. Free trial versions are available.

Source: IAR Systems

New High-Efficiency Power Supply IC Supports the Power Rules Requirements

Renesas Electronics Corporation recently announced a high-efficiency power supply IC the that supports the Power Rules requirements as defined in USB Power Delivery (USB PD) 2.0 and 3.0 specifications from the USB Implementers Forum (USB-IF). Engineers can use the RAA230161 IC with a wide variety of equipment that uses DC power, such as PC peripheral equipment, office equipment, hub applications, and more. With the IC, system manufacturers can safely implement reliable power supply equipment based on the USB PD 2.0 and 3.0 specifications.

The RAA230161 power supply IC’s features and specs:

  • Achieves an efficiency rate up to a 95% and suppresses heat generation
  • Supports the Power Rules in USB PD 2.0 and 3.0 standards
  • Includes various built-in protection functions for reliable power supply equipment in a minimal amount of space
  • Leads to higher safety and shorter development times with a variety of reference boards that include the IC and a Renesas USB PD 3.0 controller

Samples of the RAA230161 are currently. Mass production is scheduled to begin in September 2016 with a volume of 500,000 units per month.

Source: Renesas Electronics

Engineering, Consulting, & Nonstop Innovation

Engineer and author Robert Lacoste has been designing and innovating for more than two decades. Fortunately for us, Robert is also an excellent writer who regularly publishes Circuit Cellar articles on the “dark” and difficult side of engineering. Over the years, he has taught us about topics ranging from direct digital synthesis to RF mixers to bipolar transistor biasing.

This week, Robert gives us a tour of his consulting company, Alciom, which is based just outside of Paris. He also talks about his electronics equipment and his love for difficult projects.

Rugged RS-485 Transceivers for PROFIBUS-DP Networks

Linear Technology recently introduced the LTC2876 and LTC2877, which are high-voltage-tolerant RS-485 transceivers targeted for PROFIBUS-DP (decentralized periphery) networks. Whether transmitting,  receiving, in standby or powered off, the LTC2876 and LTC2877 tolerate ±60 V on their bus pins, eliminating common damage due to transmission line faults.Linear 2877
LTC2876 and LTC2877 features and specs:

  • Protected from overvoltage line faults to ±60 V
  • ±52-kV ESD Interface Pins, ±15 kV on all other pins
  • Extended common mode range: ±25 V
  • 1.65-to-5.5-V Logic supply pin for flexible digital interfacing (LTC2877)
  • 5-V Supply can operate down to 3 V for low-power, low-swing applications
  • Wide operating temperature range: –40°C to 125°C
  • Available in small DFN and MSOP packages

Source: Linear Technology 

New Synchronous Buck Regulators Offer POL Conversions

Intersil Corp. recently announced a new  family of monolithic synchronous buck regulators that step-down 5- and 3.3-V primary rails to point-of-load (POL) inputs as low as 0.6 V for GPUs, DSPs, SoCs,and FPGAs. The pin-compatible ISL78233, ISL78234, and ISL78235 deliver 3, 4, and 5 A, respectively, of continuous output current to infotainment head units and advanced driver assistance systems (ADAS). intersil isl7823

Using a current mode control architecture to deliver fast transient response and excellent loop stability, the ISL7823x synchronous step-down DC/DC converters integrate low RDSon high-side PMOS and low-side NMOS MOSFETs. Moreover,  they combine a switching frequency of 2 MHz with guaranteed 100 ns (max) minimum on time to avoid AM radio channel interference.

ISL7823x features and specifications:

  • Support input voltage range from 2.7 to 5.5 V and deliver high efficiency up to 95%
  • 100 ns guaranteed phase minimum on time for wide output regulation
  • Adjustable switching frequency from 500 kHz to 4MHz (with 2 MHz default)
  • External synchronization up to 4 MHz
  • Provide 1% reference accuracy for tight regulation
  • Soft-stop output discharge during disable
  • Fault protections  (over-temperature, over-current, output over-and under-voltage, input under-voltage lockout, short-circuit, and negative over-current)
  • AEC-Q100 qualified for operation from –40°C to 125°C
  • Wettable flank QFN package

The ISL78235 5-A synchronous buck regulator is available in a 5 mm × 5 mm 16-lead WFQFN package for $2.75 in 1,00-unit quantities. A 3 mm × 3 mm TQFN package is also available. The ISL78235EVAL2Z evaluation board costs $67.80.

The ISL78233 3-A and ISL78234 4-A synchronous buck regulators are available now in 5 mm × 5 mm 16-lead WFQFN packages. The ISL78233 costs $1.75 in 1,000-unit quantities. The ISL78234 is $1.95 in 1,000-unit quantities. The ISL78233EVAL2Z and ISL78234EVAL2Z evaluation boards cost $56 each.

Source: Intersil Corp.

New Dev Kit for Xilinx FPGA-Enabled Accelerator Cards

BittWare recently announced upcoming availability of an OpenPOWER CAPI Developer’s Kit for its Xilinx FPGA-enabled accelerator cards. The kit is intended to give you a fast way to connect the Xilinx All Programmable FPGA to a CAPI-enabled IBM POWER8 system.

The kit includes:

  • BittWare XUSP3S FPGA accelerator card, which is a ¾-length PCIe board featuring the Xilinx Virtex UltraScale VU095, four QSFPs for 4× 100 GbE, and flexible memory configurations with up to 64 GB of memory and support for Hybrid Memory Cube (HMC)
  • IBM Power Service Layer (PSL) IP to provide the connection to the POWER8 chip
  • CAPI host support library
  • An example CAPI design

 

BittWare’s OpenPOWER CAPI Developer’s Kit is scheduled to be available in Q2 2016.

Source: BittWare