About Circuit Cellar Staff

Circuit Cellar's editorial team comprises professional engineers, technical editors, and digital media specialists. You can reach the Editorial Department at editorial@circuitcellar.com, @circuitcellar, and facebook.com/circuitcellar

Trends in Custom Peripheral Cores for Digital Sensor Interfaces

Building ever-smarter technology, we perpetually require more sensors to collect increasing amounts of data for our decision-making machines. Power and bandwidth constraints require signals from individual sensors to be aggregated, fused and condensed locally by sensor hubs before being passed to a local application processor or transmitted to the cloud.

FPGAs are often used for sensor hubs because they handle multiple parallel data paths in real time extremely well and can be very low power. ADC parallel interfaces and simple serial shift register interfaces are straightforward to implement in FPGA logic. However, interfacing FPGAs with more complex serial devices—which are becoming more common as analog and digital circuitry are integrated—or serializing collected data is often less straightforward. Typically, serial interfaces are implemented in FPGA fabric as a state machine where a set of registers represents the state of the serial interface, and each clock cycle, logic executes depending on the inputs and state registers. For anything but the most trivial serial interface, the HDL code for these state machines quickly balloons into a forest of parallel if-elseif-else trees that are difficult to understand or maintain and take large amounts of FPGA fabric to implement. Iterating the behavior of these state machines requires recompiling the HDL and reprogramming the FPGA for each change which is frustratingly time consuming.

Custom soft cores offer an alternate solution. Soft cores, sometimes known as IP cores, are not new in FPGA development, and most FPGA design tools include a library of cores that can be imported for free or purchased. Often these soft cores take the form of microcontrollers such as the Cortex M1, Microblaze, lowRISC, etc., which execute a program from memory and enable applications to be implemented as a combination of HDL (Verilog, VHDL, etc.) and procedural microcode (assembly, C, C++, etc.).

While off-the-shelf soft core microprocessors are overkill and too resource intensive for implementing single serial interfaces, we can easily create our own custom soft cores when we need them that use fewer resources and are easier to program than a state machine. For the purpose of this article, a custom soft core is a microcontroller with an instruction set, registers, and peripheral interfaces created specifically to efficiently accomplish a given task. The soft core executes a program from memory on the FPGA, which makes program iteration rapid because the memory can be reprogrammed without resynthesizing or reconfiguring the whole FPGA fabric. We program the soft core procedurally in assembly, which mentally maps to serial interface protocols more easily than HDL. Sensor data is made available to the FPGA fabric through register interfaces, which we also define according to the needs of our application.

Having implemented custom soft cores many times in FPGA applications, I am presently developing an open-source example/template soft core that is posted on GitHub (https://github.com/DanielCasner/i2c_softcore). For this example, I am interfacing with a Linear Technology LTC2991 sensor that has internal configuration, status, and data registers, which must be set and read over I2C (which is notoriously difficult to implement in HDL). The soft core has 16-bit instructions defined specifically for this application and executes from block ram. The serial program is written in assembly and compiled by a Python script. I hope that this example will demonstrate how straightforward and beneficial creating custom soft cores can be.

While I have been discussing soft cores for FPGAs in this article, an interesting related trend in microprocessors is the inclusion of minion cores, sometimes also called programmable real-time units (PRUs) or programmable peripherals. While not fully customizable as in FPGA fabric, these cores are very similar to the soft cores discussed, as they have limited instruction sets optimized for serial interfaces and are intended to have simple programs that execute independently of the application to interface with sensors and other peripherals. By freeing the main processor core of direct interface requirements, they can improve performance and often simplify development. In the future, I would expect more and more MCUs to include minion cores among their peripherals.

As the amount of data to be processed and efficiently requirements increase, we should expect to see heterogeneous processing in FPGAs and microcontrollers increasing and be ready to shift our mental programming models to take advantage of the many different paradigms available.

Daniel Casner is a robotics engineer at Anki, co-founder of Robot Garden, hardware start-up adviser, and embedded systems consultant. He is passionate about building clever consumer devices, adding intelligence to objects, and smart buildings or any other cyber-physical system. His specialties include: design for manufacture and salable production; cyber-physical security; reverse engineering; electronics and firmware; signal processing; and prototype development.

This essay appears in Circuit Cellar 301.

Test Adapter for 0.5-mm Pitch LGA20

Ironwood Electronics recently introduced the PB-LGA20A-Z-01 Socket Probe Adapter, which is intended for the high-speed testing of LGA devices while accessing the signals using testers via header pins. The socket probe adapter is designed to interface with 0.5-mm pitch Fine pitch Land Grid Array (LGA) packages.C14646a Ironwood

The PB-LGA20A-Z-01’s features include:

  • shortest possible trace length for maximum speed
  • low inductance
  • low capacitance
  • blind and buried via PCB design technology

The PB-LGA20A-Z-01 test adapter costs $1,499. The LGA socket is also available individually.

Source: Ironwood Electronics

New CAN FD and FlexRay Trigger and Decode Options for WaveSurfer 3000

Teledyne LeCroy recently announced CAN FD and FlexRay, which are two new trigger and decode options for the WaveSurfer 3000 oscilloscope. You now have the necessary tools for analyzing and debugging automotive systems with the CAN FD and FlexRay serial data communication standards.TELEDYNE-CANFD

You can use the CAN FD and FlexRay trigger to isolate Frame IDs, specific data packets, remote frames, and error frames. The decodes use a color-coded overlay that enables you to identify different parts of the CAN FD and FlexRay data.

 

Both the WS3K-CAN FDbus TD and WS3K-FlexRaybus TD packages for the WaveSurfer 3000 cost $990.

Source: Teledyne LeCroy

Circuit Cellar August Issue Live

CC-2015-08-Issue-301The August 2015 issue of Circuit Cellar (#301) is now available. The issue comprises articles on the following topics: simple embedded serial communications, recording .3GPP files, image processing, wearable tech innovation, ground loops, PSoC programmable logic, embedded wireless systems, vintage electronic calculators, laser sensor exploration, and custom peripheral cores for digital sensor interfaces.

Robots with a Vision

Machine chine vision is a field of electrical engineering that’s changing how we interact with our environment, as well as the ways by which machines communicate with each other. Circuit Cellar has been publishing articles on the subject since the mid-1990s. The technology has come a long way since then. But it’s important (and exciting) to regularly review past projects to learn from the engineers who paved the way for today’s ground-breaking innovations.

In Circuit Cellar 92, a team of engineers (Bill Bailey, Jon Reese, Randy Sargent, Carl Witty, and Anne Wright) from Newton Labs, a pioneer in robot engineering, introduced readers to the M1 color-sensitive robot. The robot’s main functions were to locate and carry tennis balls. But as you can imagine, the underlying technology was also used to do much more.

The engineering team writes:

Machine vision has been a challenge for AI researchers for decades. Many tasks that are simple for humans can only be accomplished by computers in carefully controlled laboratory environments, if at all. Still, robotics is benefiting today from some simple vision strategies that are achievable with commercially available systems.

In this article, we fill you in on some of the technical details of the Cognachrome vision system and show its application to a challenging and exciting task—the 1996 International AAAI Mobile Robot Competition in Portland, Oregon… In 1996, the contest was for an autonomous robot to collect 10 tennis balls and 2 quickly and randomly moving, self-powered squiggle balls and deliver them to a holding pen within 15 min.

In M1’s IR sensor array, each LED is fired in turn and detected reflections are latched by the 74HC259 into an eight-bit byte.

In M1’s IR sensor array, each LED is fired in turn and detected reflections are latched by the 74HC259 into an eight-bit byte.

At the time of the conference, we had already been manufacturing the Cognachrome for a while and saw this contest as an excellent way to put our ideas (and our board) to the test. We outfitted a general-purpose robot called M1 with a Cognachrome and a gripper and wrote software for it to catch and carry tennis balls… M1 follows the wall using an infrared obstacle detector. The code drives two banks of four infrared LEDs one at a time, each modulated at 40 kHz.

The left half of M1’s infrared sensor array is composed of a Sharp GP1U52X infrared detector sandwiched between four infrared LEDs

The left half of M1’s infrared sensor array is composed of a Sharp GP1U52X infrared detector sandwiched between four infrared LEDs

Two standard Sharp GP1U52X infrared remote-control reception modules detect reflections. The 74HC163/74HC238 combination fires each LED in turn, and the ’HC259 latches detected reflections. This system provides reliable obstacle detection in the 8–12″ range.

The figure above shows the schematic. The photo shows the IR sensors.

The system provides only yes/no information about obstacles in the eight directions around the front half of the robot. However, M1 can crudely estimate distance to large obstacles (e.g., walls) via patterns in the reflections. The more adjacent directions with detected reflections, the closer the obstacle probably is.

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Two New PIC Families with Core-Independent Peripherals

Looking for an 8-bit microcontroller for an IoT application? Microchip Technology announced from ESC 2015 Silicon Valley two new 8-bit families that expand its growing portfolio of PIC microcontrollers with Core-Independent Peripherals (CIPs).

The PIC16F1579 and PIC16F18877 8-bit MCU families provide you with with a variety of intelligent options in low pin count packages and a wide operating voltage range.Microchip PIC16F157X

Both families offer the Peripheral Pin Select feature for flexible pin mapping and PCB routing to minimize EMI and crosstalk. Intended applications include consumer electronics, the Internet of Things (IoT), wearable technology and safety-critical systems.

The Curiosity Development Board costs $20. Pricing for the PICs starts at $0.51 each in 10,000-unit quantities.

Source: Microchip Technology

Simple Energy Profiling for IoT Applications

Silicon Labs recently announced a new release of the Simplicity Studio development platform designed to make IoT system design easier and faster. Simplicity Studio—which enables concurrent microcontroller and wireless design—features an enhanced real-time Energy Profiler tool, faster execution speed, and an easier installation process. Featuring a easy to use UI and high accuracy, the Eenergy Profiler tool will enable you to optimize your IoT designs for ultra-low energy and long battery life.image002 Simplicity Silabs

The Energy Profiler’s Energy Score feature enables you to benchmark your IoT system’s energy efficiency. With it, you can score design iterations by overall energy efficiency.

Simplicity Studio’s features and specs:

  • An Eclipse-based IDE
    Graphical configuration tools
    Energy profiling and battery estimation tools
    Network analysis tools

The latest release of Simplicity Studio with the enhanced Energy Profiler is available at: www.silabs.com/simplicity-studio.

Source: Silicon Labs

Sensor Interface Connects Multiple Sensors to MCUs or FPGAs

Exar Corp. has announced the XR10910, a new sensor interface analog front end (AFE) for the calibration of sensor outputs. The XR10910 features an onboard 16:1 differential multiplexer, offset correction DAC, programmable gain instrumentation amplifier, and voltage reference. In addition, it provides 14-bit signal path linearity and is designed to connect multiple bridge sensors to a microcontroller or FPGA with an embedded ADC.EX041_Exar

Operating from from 2.7- to 5-V supplies, the XR10910 has a wide digital supply range of 1.8 to 5 V. It typically consumes 457 µA of supply current and offers a sleep mode for reducing the supply current to 45 µA.

The XR10910 is available in a 6 mm × 6 mm QFN package. Pricing starts at $8.10 each for 1,000-piece quantities.

Source: Exar Corp.

New Radiation Hardened Multiplexers for Space Flight Data Acquisition Systems

Intersil Corp. recently launched the ISL71840SEH and ISL71841SEH, new radiation hardened (rad hard) multiplexers that offer ESD protection and high signal chain accuracy and timing performance. The ISL71840SEH 30V 16-channel multiplexer is a drop-in replacement for Intersil’s HS9-1840ARH, which has been aboard nearly every satellite and space exploration mission (e.g., NASA’s Orion flight test). For applications with form factor constraints, the ISL71841SEH offers high performance and 41% reduced board space compared with an ISL71840SEH two-chip solution.ISL71840-Intersil

Both the ISL71840SEH and ISL71841SEH offer per-switch over-voltage protection. When an input channel experiences over-voltage, the remaining channels continue sending data to the ADC. Both multiplexers provide a “cold spare” redundant capability, which enables the connection of two or three additional unpowered multiplexers to a common data bus. If needed, a redundant multiplexer is immediately activated. Both multiplexers provide a wide supply range with split-rail operation from ±10.8 V to 16.5 V and an absolute maximum of ±20 V.

Source: Intersil Corp.

AcqirisMAQS Software Simplifies Multichannel Data Acquisition Systems

Keysight Technologies recently announced a new version of its U1092A AcqirisMAQS Multichannel Acquisition Software. AcqirisMAQS software enables configuration management as well as visualization of data for hundreds of channels from a single console. The client-server architecture supports remote operation, making it possible for the data acquisition system to be distributed over a LAN. Keysight-AcqirisMAQS

A fully configurable GUI enables you to easily select instruments and measurement channels for the configuration of the acquisition parameters. Acquired data is presented in multiple display windows. Each window is fully configurable, including the selection of the number of plot areas and axes. Additional display functions provide multi-record overlay, persistence, frequency spectrum, and scalar computations on each trace. A special option for triggered single shot experiments adds an advanced configuration manager, digitizer memory protection locking and fail-safe operation.

Keysight’s multichannel digitizers contain all the timing and synchronization technologies needed to create synchronous sampling across tens or hundreds of channels at a time. For example, a reliable triggering and synchronization is essential to correctly recreate the event or process from captured data. More information about simplifying high-speed multichannel acquisition systems is available in the AcqirisMAQS Multichannel Acquisition Software Document Library.

The new version of the AcqirisMAQS multichannel acquisition software—including a 30-day free trial (evaluation mode)—is currently available now for the Keysight M9709A AXIe 8-bit high-speed digitizer as well as all the others Keysight high-speed digitizers. The 30-day free trial provides the Master and Monitoring functionality for 30 days.

Source: Keysight

Simplified IoT Connectivity with the Thread Networking Solution

Silicon Labs recently launched the Thread networking solution, which offers developers a straightforward way to develop Thread-compliant products for the Internet of Things (IoT), including thermostats, wireless sensor networks, and more. Thread provides a standards-based, low-power mesh networking solution based on IP. It enables secure and scalable Internet connectivity for battery-powered devices in connected environments. SiliconLabsThread

Silicon Labs offers a variety of mesh-networking SoCs and a common development platform for both ZigBee and Thread solutions. With the Silicon Labs Thread stack, EM35xx wireless SoC platform, and hardware and software tools, you can seemlessly migrate from ZigBee to Thread via over-the-air (OTA) upgrades. Silicon Labs’ hardware and software roadmap enable multi-protocol, multi-band 2.4-GHz and sub-GHz wireless connectivity for the IoT.

Silicon Labs offers essential development and debugging tools. Its AppBuilder tool simplifies and accelerates the development of IP-based mesh networking applications. With AppBuilder you configure mesh networking applications for Thread protocol using Silicon Labs’ application framework. A Silicon Labs Desktop Network Analyzer tool provides complete visibility of all wireless networking activity by using the unique packet trace port available in Silicon Labs’ mesh networking SoCs.

The Silicon Labs Thread software stack and sample application are available at no charge if you have a registered EM35x-DEV development kit. The EM35x-DEV kits provide a common platform for both ZigBee and Thread development, allowing you to address multiple markets. Thread modules are available now from Silicon Labs’s ecosystem partners, including California Eastern Labs (CEL) and Telegesis.

Source: Silicon Labs

New Probe Adapters for Teledyne LeCroy Oscilloscopes

Teledyne LeCroy has introduced two new adapters to support third-party probes and current measurement devices. The TPA10 TekProbe Probe Adapter adapts a wide variety of Tektronix voltage and current probes. The CA10 Current Sensor Adapter adapts a wide variety of third-party current measurement devices. Both connect to the Teledyne LeCroy ProBus probe interface that’s on most Teledyne LeCroy oscilloscopes.TELEDYNELECROY-probe-adapter

The TPA10 TekProbe Probe Adapter enables you to connect select Tektronix TekProbe interface level II probes to any ProBus-equipped Teledyne LeCroy oscilloscope. It automatically detects the Tektronix probe, supplies power and offset control to the probe, and then communicates the probe signal to the oscilloscope. Supported probes include many popular Tektronix probes, preamplifiers, current probes, single-ended active probes, and differential active probes.

With the CA10 Current Sensor Adapter, a third-party current measurement device can operate like a Teledyne LeCroy probe. It is programmable and customizable to work with third-party current measurement devices that output voltage or current signals proportional to measured current. The CA10 also provides the ability to easily install physical hardware components (e.g., shunt resistors and bandwidth filter components).

The TPA10 costs $950. The CA10 is $295. A QuadPak (four of each device) costs $3800 and $1180, respectively. The QuadPak includes a soft-carrying case to store the adapters. Delivery time for each item is four to six weeks.

Source: Teledyne LeCroy

Wireless Remote Control of the AVMux

In 1994, Circuit Cellar’s founder, Steve Ciarcia, asked: “What good is having ultimate control over your virtual audio/video environment if you have to get out of your chair to change the setup?” Great question. His answer was even better: “Outfit your home theater in style by adding an RF interface to the AVMux.”

In Circuit Cellar 46, Steve writes:

Using a couple of new chips from Maxim and Analog Devices, the AVMux facilitates effortless switching of up to eight video channels and up to eight sets of stereo audio channel pairs. Using the AVMux, I can effortlessly attach and reconfigure the connections between multiple VCRs, CD players, a Pro Logic decoder, a laserdisc player, and various other audio/video sources to the same set of amplifiers or in any number of different electronic combinations.CiarciaCC46-AVMux

With the possible exception of the actual wiring chore itself, the basic multiplexer and control unit is quite straightforward and easily constructed. Unfortunately, solving the basic switching problems only served to create further design necessities. Let me explain.

The primary problem with commercial multiplexers (when they used to be available) is that they are housed in a box much like traditional stereo equipment with all the input/output jacks on the back. Such shortsightedness on their part also requires taking a chainsaw to your expensive CWD oak stereo cabinets to widen the minuscule wire access holes to actually route all these wires.

Download the complete article.

July Electrical Engineering Challenge Live (Sponsor: NetBurner)

Ready to put your electrical engineering skills to the test? The July Electrical Engineering Challenge (sponsored by NetBurner) is live.

This month, find the error in the code posted below (and on the Challenge webpage) for a chance to win a NetBurner MOD54415 LC Development Kit ($129 value) or a Circuit Cellar Digital Subscription (1 year).

TAKE THE CHALLENGE NOW

Find the error in the code and submit your answer via the online Submission Form by the deadline: 2 PM EST on July 20, 2015. Two prize winners from the pool of respondents who submit the correct answer will be randomly selected.

Find the error in the code and submit your answer via the online Submission Form by the deadline: 2 PM EST on July 20, 2015. Two prize winners from the pool of respondents who submit the correct answer will be randomly selected.

PRIZES

Out of each month’s group of entrants who correctly find the error in the code or schematic, one person will be randomly selected to win a NetBurner IoT Cloud Kit and another person will receive a free 1-year digital subscription to Circuit Cellar.

  • NetBurner MOD54415 LC Development Kit: You can add Ethernet connectivity to an existing product or use it as your product’s core processor! The NetBurner Ethernet Core Module is a device containing everything needed for design engineers to add network control and to monitor a company’s communications assets. The module solves the problem of network-enabling devices with 10/100 Ethernet, including those requiring digital, analog, and serial control.NetburnerMod54415module
  • Circuit Cellar Digital Subscription (1 year): Each month, Circuit Cellar magazine reaches a diverse international readership of professional electrical engineers, EE/ECE academics, students, and electronics enthusiasts who work with embedded technologies on a regular basis.Circuit Cellar magazine covers a variety of essential topics, including embedded development, wireless communications, robotics, embedded programming, sensors & measurement, analog tech, and programmable logic.

RULES

Read the Rules, Terms & Conditions

SPONSOR

NetBurner solves the problem of network enabling devices, including those requiring digital, analog and serial control. NetBurner provides complete hardware and software solutions that help you network enable your devices.netburneroffer

NetBurner, Inc.
5405 Morehouse Dr.
San Diego, CA 92121 USA

How-To Guide for Timing Analysis

Although many young engineers have been taught excellent circuit design techniques, most haven’t been schooled about the importance of timing analysis. What is timing analysis? Why is timing analysis important? How do you perform timing analysis? Philip Nowe’s Circuit Cellar 160 article covers the essentials.

As a hardware designer and manager, I’ve noticed that many electrical engineering students are often missing something when they begin their first full-time jobs. They’ve been taught how to design great circuits, some of them quite complex, but they haven’t been taught the importance of timing. What does timing analysis mean? Why is timing analysis important? How is it done? In this article, I answer these questions. In addition, I present you with a real design problem that was solved with timing analysis. So, here we go!

WHY TIMING ANALYSIS?

There are a couple of reasons for performing timing analysis. First and foremost, it can be used to verify that a circuit will meet all of its timing requirements. Timing analysis can also help with component selection. An example is when you are trying to determine what memory device speed you should use with a microprocessor. Using a memory device that is too slow may not work in the circuit (or would degrade performance by introducing wait states), and using one that is too fast will likely cost more than it needs to.

A WORKING DEFINITION

Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces are met. Typically, this means that you are trying to prove that all set-up, hold, and pulse-width times are being met.

A minimum or maximum digital simulation is not actually the worst-case analysis. That is what a number of entry-level engineers believe. The worst-case analysis takes into account minimum delays through some paths and maximum delays through other paths. For instance, the worst-case set-up timing with respect to flip-flop B in Figure 1 would be the minimum delay to the clock input combined with the maximum delay to the data input of flip-flop B.

Figure 1: The simplified digital circuit contains delays in the data and the clock paths. The timing values are shown in Table 1.

Figure 1: The simplified digital circuit contains delays in the data and the clock paths. The timing values are shown in Table 1.

Let’s assume the timing values in Table 1 are for the circuit elements in Figure 1. Do you think that there is a problem with these values? Take a look at this circuit in a waveform view in Photo 1. Notice that the bottom of the photo shows the parameters used in determining the set-up time and hold timing. Red indicates that a condition has not been met. If the setup time is read and has a margin of –1, the set-up time has not been met and is off by 1 ns. The hold time indicates that there is 1-ns margin.

Table 1: Here are the timing values for the circuit illustrated in Figure 1.

Table 1: Here are the timing values for the circuit illustrated in Figure 1.

In Photo 1, the gray areas of the waveforms indicate the uncertainty of when the edge occurs. Notice that the output of logic gate 2 has the largest uncertainty, because the uncertainty is cumulative as you go through a delay chain.

Photo 1: I used Timing Diagrammer Pro for the timing analysis of the simplified digital circuit. Note that the gray areas on the waveform denote regions of uncertainty. The red areas show a timing violation.

Photo 1: I used Timing Diagrammer Pro for the timing analysis of the simplified digital circuit. Note that the gray areas on the waveform denote regions of uncertainty. The red areas show a timing violation.

So, the delay at the output of logic gate 2 is equal to the delay from CLK A to Q of flip-flop A as well as the delays through logic gates 1 and 2. Note that the waveform also uses color highlighting to indicate that constraints are not being met.

Download the entire article.