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Circuit Cellar's editorial team comprises professional engineers, technical editors, and digital media specialists. You can reach the Editorial Department at editorial@circuitcellar.com, @circuitcellar, and facebook.com/circuitcellar

Q&A: Electrical Engineer & FPGA Enthusiast

Chris Zeh is San Jose, CA-based hardware design engineer who enjoys working with FPGA development boards, application-specific integrated circuits, and logic analyzers. He recently told us about the projects he is involved with at STMicroelectronics and explained what he’s working on in his free time.

CIRCUIT CELLAR: Tell us about Idle-Logic.com. Why and when did you decide to start a blog?

ZehCHRIS: I started blogging in the winter of 2009, a little more than a year after I graduated Colorado State University with a BSEE. I realized that after graduating it was important to continue working on various projects to keep my mind and skills sharp. I figured the best way to chronicle and show off my projects was to start a blog—my little corner of the Internet.

CIRCUIT CELLAR: What types of projects do you feature on your site?

CHRIS: I like working on a wide range of different types of projects, varying from software development to digital and analog design. I’ve found that most of my projects highlighted on Idle-Logic.com have been ones focusing on FPGAs. I find these little reprogrammable, multipurpose ICs both immensely powerful and fascinating to work with.

My initial plan for the blog was to start a development project to create an FPGA equivalent to the Arduino. I wanted to build a main board with all the basic hardware to run an Altera Cyclone II FPGA and then create add-on PCBs with various sensors and interfaces. My main FPGA board was to be named the Saturn board, and the subsequent add-on “wings” were to be named after the various moons of Saturn.

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

a—Chris’s Saturn board prototype includes an Altera Cyclone II FPGA and JTAG FPGA programmer, two linear regulators, a 5-V breadboard power supply, and a 24-MHz clock. b—A side view of the board

The project proceeded nicely. I spent some time brushing up on my Photoshop skills to put together a logo and came up with a minimized BOM solution to provide power to the nine different voltage supplies, both linear regulators and switched-mode supplies. One aspect of FPGAs that can make them costly for hobbyist is that the programming JTAG cable was on the order of $300. Fortunately, there are a few more affordable off-brand versions, which I used at first. After many weeks of work, I finally had the total solution for the main FPGA board. The total cost of the prototype system was about $150. Eventually I came up with a way to bit bang the FPGA’s programming bitstream using a simple $15 USB-to-UART IC breakout board driven by a tiny Python application, eliminating the need for the pricey cable. This Future Technology Devices International FT232RL USB-to-UART IC also provided a clock output enabling me to further reduce the component count.

The project was a success in that I was compelled to completely digest the FPGA’s 470-page handbook, giving me a solid grasp of how to work with FPGAs such as the Cyclone II. The project was a failure in that the FPGA breakout board I wanted to use for the project was discontinued by the manufacturer. Creating and fabricating my own four-layer board and hand soldering the 208-pin package was both prohibitively expensive and also a little daunting.

Fortunately, at that time Terasic Technologies introduced its DE0-Nano, a $79 commercial, $59 academic, feature-packed FPGA evaluation board. The board comes with two 40-pin general I/O plus power headers, which has become a perfect alternative base platform for FPGA development. I now intend to develop add-on “wings” to work with this evaluation board.

CIRCUIT CELLAR: Tell us more about how you’ve been using Terasic Technologies’s DE0-Nano development and education board.

CHRIS: The main project I’ve been working on lately with the DE0-Nano is creating and adding support for a full-color 4.3” (480 × 272 pixel) thin- film transistor (TFT) touchscreen LCD. Because of the large pin count available and reconfigurable logic, the DE0-Nano can easily support the display. I used a Waveshare Electronics $20 display, which includes a 40-pin header that is almost but not quite compatible with the DE0-Nano’s 40-pin header. Using a 40-pin IDC gray cable, I was able to do some creative rewiring (cutting and swapping eight or so pins) to enable the two to mate with minimal effort. Eventually, once all the features are tested, I’ll fabricate a PCB in place of the cable.

There are many libraries available to drive the display, but for this project I want to develop the hardware accelerators and video pipeline from the ground up, purely though digital logic in the FPGA. I recently picked up an SD card breakout board and a small camera breakout board. Using these I would like to start playing around with image processing and object recognition algorithms.

CIRCUIT CELLAR: What do you do at STMicroelectronics and what types of projects are you working on?

CHRIS: My official title is Senior Hardware Design Engineer. This title mainly comes thanks to the first project I worked on for the company, which is ongoing—an FPGA-based serial port capture and decoding tool named the HyperSniffer. However, my main role is that of an application engineer.

I spend most of my time testing and debugging our prototype mixed-signal ASICs prior to mass production. These ASICs are built for the hard disk drive industry. They provide several switch-mode power supplies, linear regulators, brushless DC motor controllers, voice coil motor actuation, and a shock sensor digital processing chain, along with the various DACs, ADCs, and monitoring circuits all integrated into a single IC.

Our ASIC’s huge feature set requires me to stay sharp on a wide variety of topics, both analog and digital. A typical day has me down in the lab writing scripts in Python or Visual Studio, creating stimuli, and taking measurements using my 1-GHz, 10-GSPS LeCroy WavePro 7100A oscilloscope, several 6.5-digit multimeters, dynamic signal analyzers, and noise injection power supplies among other instruments. I work closely with our international design team and our customers to help discover and document bugs and streamline the system integration.

A few years back I was able to join my colleagues in writing “Power Electronics Control to Reduce Hard Disk Drive Acoustics Pure Tones,” an Institute of Electrical and Electronics Engineers (IEEE) paper published for the Control and Modeling for Power Electronics (COMPEL) 2010 conference. I presented the paper, poster, and demonstration at the conference discussing a novel technique to reduce acoustic noise generated by a spindle motor.

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent Himpe and Albino Miglialo.)

Chris designed the HyperSniffer logic analyzer, which is shown with the HyperDrive main board. (The PCB was designed by Vincent
Himpe and Albino Miglialo.)

CIRCUIT CELLAR: Tell us more about the HyperSniffer project.

CHRIS: The HyperSniffer project is an FPGA- based digital design project I first created right out of college. (My colleagues Vincent Himpe and Albino Miglialo did the board design and layout.) The tool is basically an application-specific logic analyzer. It enables us to help our customers troubleshoot problems that arise from serial port transmissions between their system-on-a-chip (SoC) and our ASIC. Through various triggering options it can collect and decode the two or three wire data transmissions, store them on on- board memory, and wait for retrieval and further processing by the application running on the PC. One of this tool’s nice features is that it is capable of synchronizing and communicating with an oscilloscope, enabling us to track down problems that happen in the analog domain that arise due to commands sent digitally.

You can read the entire interview in Circuit Cellar 290 (September 2014).

HumDT Wireless UART Data Transceiver

Linx Technologies recently announced the launch of its 11.5 mm × 14.0 mm HumDT wireless UART data transceiver with built-in networking with encryption. Each module can act as one of three components in a wireless network: an access point that controls a network, a range extender (to repeat messages and expand the network’s range, or an end device.

Linx Technologies HumDT

Linx Technologies HumDT

Each access point can connect to up to 50 range extenders and end devices. The access point also supports routing so end devices can communicate with each. The transceiver automatically manages all routing and network maintenance functions.

The 900-MHz HumDT version outputs up to 10 dBm, which results in a line-of-sight range of up to 1,600 m (1 mile), depending on the antenna implementation. The 2.4-GHz version outputs up to 1 dBm, resulting in a line-of-sight range of 100 m (300′).

To aid rapid development, the HumDT Series transceiver is available as part of a newly conceived type of Master Development System. This development kit is designed to assist in the rapid evaluation and integration of the HumDT Series data transceiver modules. The all-inclusive system features several preassembled evaluation boards, which include everything needed to quickly test the operation of the transceiver modules.

At below $9 in volume, the Hummingbird platform is a low-cost complete wideband transceiver with microcontroller module.

Source: Linx Technologies

 

WIZnet Design Challenge Winners (Sponsored)

WIZnet’s Connect the Magic 2014 Design Challenge provided electronics enthusiasts with the opportunity to use WIZnet’s WIZ550io Ethernet module in a project for a chance to win a share of $15,000 in prizes. The submission deadline was August 3, 2014, and soon thereafter the judges began scoring the entries. We’re excited to announce that the results are now in and winning projects are live.

First Prize — Chimaera: The Poly-Magneto-Phonic Theremin, Hans Peter Portner (Switzerland)

First Prize — Chimaera: The Poly-Magneto-Phonic Theremin, Hans Peter Portner (Switzerland)

You can study the complete projects (documentation, schematics, photos, code, and more) on the Winners Page. Congratulations to the following winners!

WINNING PROJECTS

  • First Prize — Chimaera: The Poly-Magneto-Phonic Theremin, Hans Peter Portner (Switzerland)
  • Second Prize — LCDTV Server: Streaming Media Using Ethernet/USB Adapter, Lindsay Meek (Australia)
  • Third Prize — WIZ Security Network, Claudiu Chiculita (Romania)
  • Honorable Mention — Sentry, David Penrose (United States)
  • Honorable Mention — Automatic Animal Feeder, Dean Boman (United States)
  • Honorable Mention — WIZpix: Connected pixel controller, Robert Gasiorowski (United States)
  • Honorable Mention — The Instrument of Things, Radko Bankras (The Netherlands)
  • Honorable Mention — Radio Telescope Controller, Clayton Gumbrell (Australia)

    Honorable Mention — WIZpix: Connected pixel controller, Robert Gasiorowski (United States)

    Honorable Mention — WIZpix: Connected pixel controller, Robert Gasiorowski (United States)

WIZNET TECHNOLOGY

WIZnet’s WIZ550io is an excellent module for rapidly developing ’Net-enabled systems. It is an auto-configurable Ethernet controller module that includes the W5500 (TCP/IP-hard-wired chip and PHY embedded), a transformer, and an RJ-45 connector.

The WIZ550io has a unique, embedded real MAC address and auto network configuration capability. When powered up, the WIZ550io initializes itself with the MAC and default IP address and can be pinged from your computer. You don’t need to write MAC and network information such as an IP address, subnet mask, and gateway address.

The W5500 chip is a hardwired TCP/IP embedded Ethernet controller that enables Internet connection for embedded systems using Serial Peripheral Interface (SPI).

WaveSurfer 3000 Oscilloscopes with MAUI

Teledyne LeCroy recently introduced the WaveSurfer 3000 series of oscilloscopes. The series features the MAUI advanced user interface, which “integrates a deep measurement toolset and multi-instrument capabilities into a cutting edge user experience centered on a large 10.1” touch screen,” the company stated in a release.

Source: Teledyne LeCroy

Source: Teledyne LeCroy

Essential characteristics, specs, and features include:

  • Bandwidths from 200 MHz to 500 MHz, with 10 Mpts/ch memory and up to 4 GS/s sample rate.
  • Multi-instrument capabilities such as waveform generation, protocol analysis, and logic analysis
  • 130,000 waveforms/second with waveform update, as well as waveform playback and WaveScan search/find
  • An advanced active probe
  • A comprehensive toolset featuring powerful math and measurement capabilities, sequence mode segmented memory, and LabNotebook

The WaveSurfer 3000 is available in four different models (200 MHz, two-channel to 500 MHz, four-channel) with prices ranging from $3,200 to $6,950.

Source: Teledyne LeCroy

Free IAR Seminiars at ARM TechCon

IAR Systems will host two seminar days during ARM TechCon 2014 in Santa Clara, CA on October 1 and 2, 2014. The free seminars will include lectures and hands-on training.

On October 1, IAR Systems will offer five sessions (11:00 am to 4:50 pm) on topics such as: Mastering Stack and Heap for System Reliability; Safety Traps in Embedded Software Engineering; Runtime Analysis Demystified; Advanced Debugging Techniques; and Efficient Programming. On October 2, IAR Sysetms will offer sessions within the technical training program IAR Academy.

For more information, go to www.iar.com/atc2014.