Promoter Group Announces USB 3.2 Spec Update

The USB 3.0 Promoter Group has announced the pending release of the USB 3.2 specification, an incremental update that defines multi-lane operation for new USB 3.2 hosts and devices, effectively doubling the bandwidth to extend existing USB Type-C cable performance. During the upcoming USB Developer Days 2017 event, the promoters will provide detailed technical training covering USB 3.2, fast charging advancements in USB Power Delivery, and other topics.

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While USB hosts and devices were originally designed as single-lane solutions, USB Type-C cables were designed to support multi-lane operation to ensure a path for scalable performance. New USB 3.2 hosts and devices can now be designed as multi-lane solutions, allowing for up to two lanes of 5 Gbps or two lanes of 10 Gbps operation. This enables platform developers to continue advancing USB products by effectively doubling the performance across existing cables. For example, a USB 3.2 host connected to a USB 3.2 storage device will now be capable of realizing over 2 GB/sec data transfer performance over an existing USB Type-C cable that is certified for SuperSpeed USB 10 Gbps.

Key characteristics of the USB 3.2 solution include:

– Two-lane operation using existing USB Type-C cables

– Continued use of existing SuperSpeed USB physical layer data rates and encoding techniques

– Minor update to hub specification to address increased performance and assure seamless transitions between single and two-lane operation

For users to obtain the full benefit of this performance increase, a new USB 3.2 host must be used with a new USB 3.2 device and the appropriate certified USB Type-C cable. This update is part of the USB performance roadmap and is specifically targeted to developers at this time. Branding and marketing guidelines will be established after the final specification is published. The USB 3.2 specification is now in a final draft review phase with a planned formal release in time for the USB Developer Days North America event in September 2017.

The USB 3.0 Promoter Group, comprised of Apple, Hewlett-Packard, Intel Corporation, Microsoft Corporation, Renesas Electronics, ST Microelectronics, and Texas Instruments, continues to develop the USB 3.x family of specifications to meet the market needs for increased functionality and performance in SuperSpeed USB solutions. Additionally, the USB 3.0 Promoter Group develops specification addendums (USB Power Delivery, USB Type-C, and others) to extend or adapt its specifications to support more platform types or use cases where adopting USB 3.x technology will be beneficial in delivering a more ubiquitous, richer user experience.

USB 3.0 Promoter Group | www.usb.org

Don’t Miss Circuit Cellar’s Analog & Power Newsletter

Analog & Power is where stuff gets real. Converting signals to and from analog is how embedded devices interact with the real world. And without power supplies and power conversion, electronic systems can’t do anything. Circuit Cellar’s Analog & Power MFG_IB048E096T40N1-00themed newsletter is coming to your inbox tomorrow.

This newsletter content zeros in on the latest developments in analog and power technologies including DC-DC converters, AD-DC converters, power supplies, op-amps, batteries and more.

               Already a Circuit Cellar Newsletter subscriber? Great!
You’ll get your “Analog & Power” themed newsletter issue tomorrow.

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Remember, our new enhanced weekly CC Newsletter will switch its theme each week, so look for these in upcoming weeks:

Microcontroller Watch. This newsletter keeps you up-to-date on latest microcontroller news. In this section, we examine the microcontrollers along with their associated tools and support products.

IoT Technology Focus. The Internet-of-Things (IoT) phenomenon is rich with opportunity. This newsletter tackles news and trends about the products and technologies needed to build IoT implementations and devices.

Embedded Boards. This content looks at embedded board-level computers. The focus here is on modules—Arduino, Raspberry Pi, COM Express, and other small-form-factor —that ease prototyping efforts and let you smoothly scale up production volumes.

Tensilica HiFi 3z DSP IP Core Provides Enhanced Voice and Audio Processing

Cadence Design Systems has announced the Cadence Tensilica HiFi 3z DSP IP core for system-on-chip (SoC) designs targeted for the latest mobile and home entertainment applications, including smartphones, augmented reality (AR)/3D goggles, digital TVs and set-top boxes (STBs). The new HiFi 3z architecture offers more than 1.3X better voice and audio processing performance than its predecessor, the HiFi 3 DSP, which leads the industry in the number of audio DSP cores shipped.

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Higher voice sample rates require more complex voice pre-processing. Enhanced Voice Services (EVS), the latest mobile voice codec supporting voice over LTE (VoLTE), supports up to a 48kHz sample rate, compared to 16kHz for the previous AMR-WB codec. The new HiFi 3z DSP delivers more than 1.3X better performance for EVS than the HiFi 3 DSP core. Home entertainment is driving a similar workload increase as audio codecs like Dolby AC-4 and MPEG-H transition from channel-based to object-based. In addition, audio post-processing functions such as Waves Nx 3D/AR audio and the immersive audio of Dolby Atmos-enabled TVs are driving higher complexity signal processing. The HiFi 3z DSP provides more than 1.4X better performance on Dolby Atmos-enabled TVs than the HiFi 3 DSP.

The HiFi 3z DSP offers a number of architecture and instruction set architecture (ISA) improvements over the earlier HiFi 3 DSP, including:

– Dual load/store

– Advanced FLIX bundling (multiple-base ISA operations per cycle)

– Double the MACs for 16×16 (octal MAC)

– Enhanced ISA for accelerating FFTs, FIRs and IIRs

– New instruction extensions to improve codec (especially EVS) performance for mobile

– 4-way, 8-bit load for improved voice trigger performance

– 8-way, 8-bit load for reduced neural network memory usage

Tensilica HiFi DSPs are the most widely licensed audio/voice/speech processors, with support for over 200 proven software packages and more than 95 software partners in the Tensilica Xtensions partner program. More than 75 top-tier semiconductor companies and system OEMs have selected Tensilica HiFi DSPs for their audio, voice and speech products.

Cadence | www.cadence.com/go/hifi3z

PC/104-Plus SBC Features On-Board TPM Security

Versalogic is now shipping the “Liger”-a new high-performance PC/104-Plus single board computer (SBC). Based on Intel’s Kaby Lake processor, Liger combines high performance processing and high performance video with moderate power consumption (12 to 14 W typical). It features hardware-level security using an on-board Trusted Platform Module (TPM) security chip, and backwards compatibility with systems using PC/104-Plus (ISA or PCI) expansion.

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Liger is designed for applications which require extreme CPU and video processing performance in a compact 108 x 96 mm (4.3 x 3.8″) PC/104 footprint.The Liger’s on-board TPM security chip can lock out unauthorized hardware and software access. It provides a secure “Root of Trust” processing environment for defense, medical, and industrial applications that require hardware-level security functions. Additional security is provided through built-in AES (Advanced Encryption Standard) instructions.

Versalogic | www.versalogic.com

Power Analysis of a Software DES Encryption Routine

This article continues the foray into breaking software security routines, now targeting a software implementation of DES. This builds on a previous example of breaking a hardware AES example.

By Colin O’Flynn

In the previous column, I broke a simple XOR password check using side-channel power analysis. How can we apply this to more complex algorithms though? In my Circuit   Cellar   313   (August   2016) story, I demonstrated how to break the AES encryption standard running on a FPGA.

The EFF’s “Deep Crack” board could brute force a DES key in a matter of days. (Photo courtesy of Electronic Frontier Foundation)

The EFF’s “Deep Crack” board could brute force a DES key in a matter of days. (Photo courtesy of Electronic Frontier Foundation)

While I originally considered breaking a software implementation of AES in this column, there was just too much overlap between those columns. So instead I decided to pick on something new. This time, I’ll cover how we can break a software implementation of DES. The actual process ends up being very similar. But by using a different algorithm, it might help give you a bit of perspective on how the underlying  attack  works.  ….

Read this article in the August 325 issue of Circuit Cellar

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Or purchase the August 2017 issue at the  CC-Webshop

 

How-To Guide for Timing Analysis

Although many young engineers have been taught excellent circuit design techniques, most haven’t been schooled about the importance of timing analysis. What is timing analysis? Why is timing analysis important? How do you perform timing analysis? Philip Nowe’s Circuit Cellar 160 article covers the essentials.

As a hardware designer and manager, I’ve noticed that many electrical engineering students are often missing something when they begin their first full-time jobs. They’ve been taught how to design great circuits, some of them quite complex, but they haven’t been taught the importance of timing. What does timing analysis mean? Why is timing analysis important? How is it done? In this article, I answer these questions. In addition, I present you with a real design problem that was solved with timing analysis. So, here we go!

WHY TIMING ANALYSIS?

There are a couple of reasons for performing timing analysis. First and foremost, it can be used to verify that a circuit will meet all of its timing requirements. Timing analysis can also help with component selection. An example is when you are trying to determine what memory device speed you should use with a microprocessor. Using a memory device that is too slow may not work in the circuit (or would degrade performance by introducing wait states), and using one that is too fast will likely cost more than it needs to.

A WORKING DEFINITION

Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces are met. Typically, this means that you are trying to prove that all set-up, hold, and pulse-width times are being met.

A minimum or maximum digital simulation is not actually the worst-case analysis. That is what a number of entry-level engineers believe. The worst-case analysis takes into account minimum delays through some paths and maximum delays through other paths. For instance, the worst-case set-up timing with respect to flip-flop B in Figure 1 would be the minimum delay to the clock input combined with the maximum delay to the data input of flip-flop B.

Figure 1: The simplified digital circuit contains delays in the data and the clock paths. The timing values are shown in Table 1.

Figure 1: The simplified digital circuit contains delays in the data and the clock paths. The timing values are shown in Table 1.

Let’s assume the timing values in Table 1 are for the circuit elements in Figure 1. Do you think that there is a problem with these values? Take a look at this circuit in a waveform view in Photo 1. Notice that the bottom of the photo shows the parameters used in determining the set-up time and hold timing. Red indicates that a condition has not been met. If the setup time is read and has a margin of –1, the set-up time has not been met and is off by 1 ns. The hold time indicates that there is 1-ns margin.

Table 1: Here are the timing values for the circuit illustrated in Figure 1.

Table 1: Here are the timing values for the circuit illustrated in Figure 1.

In Photo 1, the gray areas of the waveforms indicate the uncertainty of when the edge occurs. Notice that the output of logic gate 2 has the largest uncertainty, because the uncertainty is cumulative as you go through a delay chain.

Photo 1: I used Timing Diagrammer Pro for the timing analysis of the simplified digital circuit. Note that the gray areas on the waveform denote regions of uncertainty. The red areas show a timing violation.

Photo 1: I used Timing Diagrammer Pro for the timing analysis of the simplified digital circuit. Note that the gray areas on the waveform denote regions of uncertainty. The red areas show a timing violation.

So, the delay at the output of logic gate 2 is equal to the delay from CLK A to Q of flip-flop A as well as the delays through logic gates 1 and 2. Note that the waveform also uses color highlighting to indicate that constraints are not being met.

Download the entire article.

Crowd Funded Arduino Board Measures 0.5. x 0.5 Inches

Crowd funded via Crowd Supply, a project called µduino is an Arduino measuring in at 12mm (0.5 inches) x 12mm. While similarly sized micro-controller boards do exist, their power is severely limited to using chips such as the Attiny85 (with up to 6 I/O ports). The µduino makes use of the power of the ATMEGA32U4 chip found in the Arduino Leonardo (a board over 20 times larger), offering 20 I/O ports, including PWM and ADC ports. In addition, the µduino can be powered by batteries or directly by micro-USB. The µduino can also operate in one of two power modes, 3.3V or 5V, which can be selected using a jumper on the board. This way, users can tailor µduino to match their sensors and power supplies.

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The prototype measures 14mm (0.55 inches) square, and the final design measures just 12mm (0.47 inches) square. Unlike many other Arduino-based boards, the µduino uses smaller hole separation (1.27mm vs 2.54mm). While vastly cutting down on size, standard sized wires are still compatible and can be soldered fairly easily.

Crowd Supply | www.crowdsupply.com/uduino

3 W Isolated DC-DC Converter Series Delivers 4:1 Input Range, Compact Package

CUI’s Power Group has announced the addition of a new 3 W isolated DC-DC converter series to its portfolio of low power DC-DC converters. The PQME3 series housed in a compact, industry standard 14 pin surface mount package measuring 0.76 x 0.71 x 0.40 in (19.20 x 18.10 x 10.16 mm), provides a rugged, low power solution for a variety of industrial, test and measurement, and telecommunication applications, thanks to its encapsulated design.

CUI PQME3-Print

Ideal for converting and isolating fluctuating dc voltages, the 3 W series features 4:1 input ratio ranges of 9 to 36 Vdc and 18 to 75 Vdc, single regulated outputs of 3.3, 5, 9, 12, 15, and 24 Vdc, remote on/off control, and 1500 Vdc input to output isolation. For devices where energy consumption is a concern, the PQME3 series offers efficiency up to 84% and no-load power draw less than 0.1 W. Operating temperatures range from -40 up to +71°C at full load, derating to 60% load at +85°C, making the low power modules suitable for harsh environments.

The 3 W isolated dc-dc converters also meet CISPR22/EN55022 Class B limits for conducted and radiated emissions, while carrying over current and short circuit protections as well as a minimum MTBF of 1,000,000 hours at +25°C ambient, calculated per MIL-HDBK-217F. The PQME3 series is available immediately with prices starting at $10.76 per unit at 200 pieces through distribution.

CUI | www.cui.com

RISC-V and Moore’s Law : An Interview with Krste Asanovic

During his busy sabbatical, Krste Asanovic took time to share his thoughts on developments n the world of processors and the open sourcing of processor architecture.

Moore’s Law and the Chip Industry’s Perfect Storm

By Wisse Hettinga

With the end of Moore’s Law in sight and a silicon manufacturing world that is struggling to protect their investments, the RISC-V foundation is throwing its nets out on the other side of the boat. How? By creating an opensource platform for future new silicon development.

“There is a lot of friction in the market,” Asanovic explains. Being a professor at Berkeley University in Computer Architecture, he knows what he is talking about. “With RISC-V we want to reduce this friction in the industry. One of the problems is the IP protection and business involvement in the industry. With SiFive you don’t have to deal with complicated contracts. Users can just come and take the material that’s all published and open source and use it in their future chip design.”

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Krste Asanovic is a SiFive founder and Professor of Computer Architecture at Berkeley University.

“The Barcelona Computer Centre is showing great interest in what we are doing with RISC-V. And the UPC computer architecture department is one of the strongest architecture group in Europe. Here—and also in the rest of Europe—there is a lot of interest in RISC-V for research projects and also for possible industrial use,” says Asanovic.

HETTINGA: Can you explain what RISC-V is?

ASANOVIC: RISC-V is an instruction set architecture (ISA). An ISA is what you use to encode software to run on hardware. In the industry there are common standards like the x86 from Intel and AMD. There’s also the ARM architecture we all know from our mobile phones and tablets. RISC-V uses different encoding which is meant to be free and open so that everyone can use without paying license fee—which is unlike the existing proprietary standards. Our goal is to have an open standard anybody can use.

HETTINGA: And what’s the level of interest from the market today for RISC-V?

ASANOVIC: If you look at the market, the x86 architecture is dominant in desktops and servers. ARM is dominant in mobile phones and tablets—and it will probably remain so. But what is interesting is that there are always new markets coming along: IoT (Internet of Things) and automotive are big markets. At the high-end of the market we see storage controllers and machine learning accelerators. These are all new greenfield areas where people are looking at new chip designs. They don’t have a large legacy of software and they are open to a new instruction set—particularly ones that are free of all sorts of legal and financial strings and give them flexibility to bring new things into the controller architecture.

HETTINGA: Give us a little history of RISC and of RISC versus CISC.

ASANOVIC: The RISC architecture goes a long way back and it’s still alive. I trace the roots of RISC way back to Seymour Cray’s early machines—like the CDC 6600—from 1964. RISC machines are register rich and have a load/store architecture. They have a lot of general registers and all operations are between registers except for the memory operations. That style of machine has remained popular for over 50 years and has outlived Moore’s Law.

Meanwhile, CISC has also been around for some time. CISC was a product of the time before integrated silicon started replacing the vacuum tubes and magnetic core memory systems. It is interesting to see that over the last couple decades there has been very little new development in the CISC architecture arena. I think everyone will agree that if you start from scratch, CISC is not a great idea.

RISC-V follows the heritage of the earlier RISC processor designs developed at Berkeley University. “RISC-V” means it is the fifth generation. We started on the project in 2010 and we were tired of using commercial ISAs for research. They were sometimes too complicated for what we wanted to do, and with the IP entanglements it is very difficult to share that research with others.

As academics, we like to share our work with others. We realized we did not want to invest in proprietary architectures. Also, a lot of commercial products are not that good. There was a quality problem and we thought we could do a lot better.

The response was overwhelming and very quickly it was getting too big for Berkeley and we started the RISC-V foundation. The goal of the foundation is to maintain the RISC-V ISA standard and we have grown to over 60 companies—including the biggest names like Qualcomm, Samsung, Microsoft, Western Digital, IBM and Google.

HETTINGA: From there, how did RISC-V lead to the creation of the SiFive organization?

ASANOVIC: At Berkeley we’ve done a great deal of research into RISC architecture, involving teams and activities. They did implementations, ported the compilers and Linux and got other operating systems up and running. Having a ‘critical mass’ of graduate students working on this project allowed people from outside to pick it up and do real work with it. It started off as an idea to have a consultancy activity around RISC-V. The co-founders—Andrew Waterman and Yunsup Lee—soon realized the opportunity and that’s why I also decided to get involved as a founder.

HETTINGA: This seems to be a very significant time in the semiconductor industry. How would you characterize where we’re at today?

ASANOVIC: The semiconductor industry is in this perfect storm where we see that Moore’s Law is ending and that new technologies and developments are getting more and more expensive. There are fewer and fewer companies capable of pulling off a new design and making money out of it. At the same time there is a growth in demand for custom chips. Everybody is talking about the Internet of Things and all those devices will need a processor—and that cannot be the same processor for all solutions. There will be a growth in silicon products, but that growth will be in many fragmented markets. The old semiconductor business model—having one design and selling many millions of it— doesn’t work anymore. That has worked with the traditional computer and mobile phone markets, but the future will see perhaps hundreds of designs in lower volumes.

With SiFive we try to figure out how this works. The traditional users of the chips are now becoming the new manufacturers. Google. Microsoft, Amazon and a lot of other companies will design and make their own chips—not to sell to others, but to use them in their own products. It will allow them to add capabilities that are not available in standard off-the-shelf chips.

Our mission is to find out if we can help smaller companies and startups to do custom silicon design and invent new products with new capabilities. We believe there is a lot of untapped innovation there. But the problem is the barrier to enter custom silicon design is too high and those great ideas do not become a product. Solving that problem is the goal of SiFive.

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SiFive’s RISC-V Arduino board makes it easy for small companies to get started with new designs.

HETTINGA: Tell us about SiFive’s RISC-V Arduino reference design board.

ASANOVIC: Our business model is to do quick developments of new chipsets and help the client to get into production at very low costs. To enable that, we made an Arduino board (at the time of the interview the new Arduino Cinque was introduced / WH) that runs very fast. And by putting it into the Arduino format a lot of small design companies will see it and can use it for new designs. The interesting thing about this product is that it will take the focus from the board to the chip level. Not only the board is open source but the chip design is too. That can open up completely new perspectives for makers, start-up companies and medium-sized businesses. All the design files of the chip are open source are on Github. This is unique in the semiconductor business. With SiFive we want to get rid of the friction in the industry. We don’t have a costly structure with NDAs and lawyers. A lower cost structure will also mean lower costs for our clients. You can come and take the designs as they are and use them.

SiFive | www.sifive.com

Dev Kit Enables Cars to Express Their Emotions

Renesas Electronics has announced that it has developed a development kit for its R-Car that takes advantage of “emotion engine”, an artificial sensibility and intelligence technology pioneered by cocoro SB Corp. The new development kit enables cars with the sensibility to read the driver’s emotions and optimally respond to the driver’s needs based on their emotional state.

The development kit includes cocoro SB’s emotion engine, which was developed leveraging its sensibility technology to recognize emotional states such as confidence or uncertainty based on the speech of the driver. The car’s response to the driver’s emotional state is displayed by a new driver-attentive user interface (UI) implemented in the Renesas R-Car system-on-chip (SoC). Since it is possible for the car to understand the driver’s words and emotional state, it can provide the appropriate response that ensures optimal driver safety.

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As this technology is linked to artificial intelligence (AI) based machine learning, it is possible for the car to learn from conversations with the driver, enabling it to transform into a car that is capable of providing the best response to the driver. Renesas plans to release the development kit later this year.

Renesas  demonstrated its connected car simulator incorporating the new development kit based on cocoro SB’s emotion engine at the SoftBank World 2017 event earlier this month in held by SoftBank at the Prince Park Tower Tokyo.

Renesas considers the driver’s emotional state, facial expression and eyesight direction as key information that combines with the driver’s vital signs to improve the car and driver interface, placing drivers closer to the era of self-driving cars. For example, if the car can recognize the driver is experiencing an uneasy emotional state, even if he or she has verbally accepted the switch to hands free autonomous-driving mode, it is possible for the car to ask the driver “would you prefer to continue driving and not switch to autonomous-driving mode for now?” Furthermore, understanding the driver’s emotions enables the car to control vehicle speed according to how the driver is feeling while driving at night in autonomous-driving mode. By providing carmakers and IT companies with the development kit that takes advantage of this emotion engine, Renesas hopes to expand the possibilities for this service model to the development of new interfaces between cars and drivers and other mobility markets that can take advantage of emotional state information. Based on the newly-launched Renesas autonomy, a new advanced driving assistance systems (ADAS) and automated driving platform, Renesas enables a safe, secure, and convenient driving experience by providing next-generation solutions for connected cars.

Renesas Electronics America | www.renesas.com

Don’t Miss Circuit Cellar’s Newsletter: Embedded Boards

Board-level embedded computers are a critical building block around which system developers can build all manor of intelligent systems. Circuit Cellar’s Embedded Boards themed newsletter is coming to your inbox tomorrow. COM Express mm

The focus here is on module types like Arduino, Raspberry Pi, COM Express, and other small-form-factor modules that ease prototyping efforts and let you smoothly scale up to production volumes.

Already a Circuit Cellar Newsletter subscriber? Great!
You’ll get your “Embedded Boards” themed newsletter issue tomorrow.

Not a Circuit Cellar Newsletter subscriber?
Don’t be left out! Sign up now:

Remember, our new enhanced weekly CC Newsletter will switch its theme each week, so look for these in upcoming weeks:

Analog & Power. This newsletter content zeros in on the latest developments in analog and power technologies including DC-DC converters, AD-DC converters, power supplies, op-amps, batteries, and more.

Microcontroller Watch. This newsletter keeps you up-to-date on latest microcontroller news. In this section, we examine the microcontrollers along with their associated tools and support products.

IoT Technology Focus. The Internet-of-Things (IoT) phenomenon is rich with opportunity. This newsletter tackles news and trends about the products and technologies needed to build IoT implementations and devices.

Software Targets Data Acq for Desktop Python under Linux

Microstar Laboratories has released DAPtools for Python software, an API that enables high-performance data acquisition applications using the Python programming language on desktop GNU/Linux systems. This is not a reduced or specialized language variant—it supports the complete, full-featured Python environment and complements the Accel64 for Linux software that provides access to DAP board features and functions. Typical applications are one-time diagnostic tests, academic research, and automatically-configurable scripting for test automation.

MicroStar

The DAPIO programming interface behind DAPtools for Python provides the same stable DAPL system services that all other high-level programming environments have used over the last 20 years. Access to that interface is through a Linux dynamic library, which Python applications can load and access using the ctypes library. DAPtools for Python presents the low-level interface as a simple “interface object” and some utility functions to make the DAP board interactions work like familiar Python objects and functions. The programming is a lot like connecting to a networked resource: open a connection, specify the data acquisition actions required, run the configuration, take the requested data, and close the connection when finished.

Microstar Laboratories | www.mstarlabs.com

NXP to Make Security Chips in its US Facilities

NXP Semiconductors has announced a $22 million dollar program that expands its operations in the United States, enabling the Company’s US facilities to manufacture security chips for government applications that can support critical US national and homeland security programs. Upon completion of the expansion project, NXP facilities in Austin, TX and Chandler, AZ will be certified to manufacture finished products that exceed the highest domestic and international security and quality standards.

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NXP R&D manufacturing facilities in San Jose, Austin and Chandler have also undergone a thorough security site certification process to produce Common Criteria EAL6+ SmartMX microcontroller family products. Common Criteria is an international set of guidelines and specifications developed for evaluating information security products to ensure they meet a rigorous security standard for government deployments.

NXP’s SmartMX microcontroller platform is designed for highly secure and fast data transactions. It is ,a proven solution for contact, contactless and dual interface applications. with over six billion ICs deployed in the field. It secures transactions for over one-third of chip-based payment cards in circulation, serving banks all over the world.

More SmartMX info:

  • It serves as the core component in a variety of digital identity schemes and is deployed in nearly 120 out of 145 countries implementing e-Government programs.
  • Used in many sovereign electronic documents such as ePassports, citizen cards, national ID cards, driving licenses, social security cards and health cards.
  • SmartMX is the 6th generation in the market, with NXP holding the most security certificates in the industry.
  • It is the preferred technology for the secure element of NFC-enabled phones.

 

NXP Semiconductors | www.nxp.com

The Most Technical

Input Voltage

–Jeff Child, Editor-in-Chief

JeffHeadShotIt is truly a thrill and an honor for me to be joining the Circuit Cellar team as the magazine’s new Editor-in-Chief. And in this—my first editorial in my new role—I want to seize the opportunity to talk about Circuit Cellar. A lot of factors attracted me to this publication. But in a nutshell its position in the marketplace is compelling. It intersects with two converging trends happening in technology today.

First, there’s the phenomenon of the rich set of tools, chips, and information resources available today. They put more power into the hands of makers and electronics DIY experts than ever before. You’ve got hardware such as Arduino and Raspberry Pi. Open source software ranging from Linux to Eclipse make integrating and developing software easier than ever. And porting back and forth between open source software and commercial embedded software is no longer prohibitive now that commercial software vendors are in a “join them, not beat them” phase of their thinking. Easy access has even reached processors thanks to the emergence of RISC-V for example (click here for more). Meanwhile, powerful FPGA chips enable developers to use one chip where an entire board or box was previously required.

The second big trend is how system-level chip technologies—like SoC-style processors and the FPGAs I just mentioned—are enabling some of the most game-changing applications driving today’s markets: including commercial drones, driverless cars, Internet-of-Things (IoT), robotics, mobile devices and more. This means that exciting and interesting new markets are attracting not just big corporations looking for high volume play, but also small start-up vendors looking to find their own niche within those market areas. And there are a lot of compelling opportunities in those spaces. Ideas that start as small embedded systems projects can—and are—blossoming into lucrative new enterprises.

What’s so exciting is that Circuit Cellar readers are at the center of both those two trends. There’s a particular character this magazine has that separates it from other technology magazines. There are a variety of long-established publications that cover electronics and whose stated missions are to serve engineers. I’ve worked for some of them, and they all have their strengths. But you can tell just by looking at the features and columns of Circuit Cellar that we don’t hold back or curtail our stories when it comes to technical depth. We get right down to the bits and bytes and lines code. Our readers are engineers and academics who want to know not only the rich details of a microcontroller’s on-board peripherals, but also how other like-minded geeks applied that technology to their DIY or commercial project. They want to know if the DC-DC converter they are considering has a wide enough input voltage to serve their needs.

Another cool thing for me about Circuit Cellar is the magazine’s origin story. Back when I was in high school and in my early days studying Computer Science in college, Steve Ciarcia had a popular column called Circuit Cellar in BYTE magazine. I was a huge fan of BYTE. I would take my issue and bring it to a coffee shop and read it intently. (Mind you this was pre-Internet. Coffee shops didn’t have Wi-Fi.) What I appreciated most about BYTE was that it had far more technical depth than the likes of PC World and PC Computing. I felt like it was aimed at a person with a technical bent like myself. When Steve later went on to found this magazine—nearly 30 years ago—he gave it the Circuit Cellar name but he also maintained that unique level of technical depth that entices engineers.

With all that in mind, I plan to uphold the stature and legacy in the electronics industry that I and all of you have long admired about Circuit Cellar. We will work to continue being the Most Technical information resource for professional engineers, academics, and other electronics specialists world-wide. Meanwhile, you can look forward to expanded coverage of those exciting market-spaces I discussed earlier. Those new applications really exemplify how embedded computing technology is changing the world. Let’s have some fun.

Bluetooth SIG Adds Mesh Networking to BLE Ecosystem

The Bluetooth Special Interest Group (SIG) announced that the wireless connectivity global standard now supports mesh networking. This enables many-to-many (m:m) device communications and is optimized for creating large-scale device networks, ideally suited for building automation, sensor networks and smart home solutions where tens, hundreds, or thousands of devices need to reliably and securely communicate with one another.

According to the Bluetooth SIG, Bluetooth Low Energy (LE) enables short-burst wireless connections and supports multiple network topologies, now including a mesh topology for establishing many-to-many (m:m) device communications. This is an important evolution for Bluetooth technology, and one of the most anticipated features envisaged by the Bluetooth SIG promoters, anticipating Bluetooth 5 practical implementations.

With this update the typical point-to-point, star-based network topology evolves directly to a true mesh networking topology, paving the way for a wide range of applications that span from personal area network solutions all the way to an expanded range of connected devices, theoretically without physical limits.

One of the main benefits will be precisely in the area where until now only standard 802.11 Wi-Fi solutions were available, which is the smart home and smart buildings. With the combination of Bluetooth 5 and mesh networking technology, manufacturers will be able to surpass worries about coverage range, without compromising on the low-power requirements that are mandatory in battery operated devices. This enables the creation of “blanket” Bluetooth networking coverage, with devices connecting between themselves without the need for a central router. This allows effectively the creation of autonomous Bluetooth Wireless Local Area Networks, allowing devices to communicate locally. For example, sensors will be able to send messages to main devices, allowing the music to start playing in the living room, as soon as the user moves out of the room.

As the Bluetooth SIG highlights, mesh networking doesn’t require any special controllers or hub equipment, there is no single point of failure, and any Bluetooth control device will be able to remote control any point of the network. All this, with assured interoperability and without complexity, allowing users to acquire and add devices from any vendor that adopted the standard.

The potential of mesh networking also allows more complex commercial and industrial scenarios. Bluetooth mesh is optimized for creating large-scale device networks and is ideally suited for building automation, sensor network, asset tracking solutions. New control and automation systems, from lighting to heating/cooling to security, wireless sensor networks (WSN) for industrial applications, are some obvious candidates for  Bluetooth mesh networking technology.

Capable of supporting broadcast topology, Bluetooth LE became an attractive alternative for asset tracking over active RFID. The addition of mesh networking lifs Bluetooth LE range limitations and establishes the adoption of Bluetooth asset tracking solutions for use in larger and more complex building environments.

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A unique full-stack approach that defines the low-level radio up to the high-level application layer, ensuring all aspects of the technology are fully specified for the updated specification. Comprehensive, multi-vendor interoperability testing is conducted during the specification development process, not after specification release, and Bluetooth SIG members can benefit of all the qualification tools and processes needed to ensure global, multi-vendor interoperability.

The Bluetooth mesh specification is now available to all members, allowing manufacturers to start prototyping products. The Bluetooth mesh networking specifications, as well as the tools required to qualify Bluetooth products with mesh networking support, are now available at the Bluetooth website. Bluetooth mesh networking operates on Bluetooth Low Energy (LE) and is compatible with core specification version 4.0 and higher.

Bluetooth SIG | www.bluetooth.com