The Future of Hardware Design

The future of hardware design is in the cloud. Many companies are already focused on the Internet of Things (IoT) and creating hardware to be interconnected in the cloud. However, can we get to a point where we build hardware itself in the cloud?

Traditional methods of building hardware in the cloud recalls the large industry of EDA software packages—board layouts, 3-D circuit assemblies, and chip design. It’s arguable that this industry emphasizes mechanical design, focusing on intricate chip placement, 3-D space, and connections. There are also cloud-based SPICE simulators for electronics—a less-than-user-friendly experience with limited libraries of generic parts. Simulators that do have a larger library also tend to have a larger associated cost. Finding exact parts can be a frustrating experience. A SPICE transistor typically does not have a BOM part number requiring a working design to become a sourcing hunt amongst several vendor offerings.123D Circuits with Wifi Module

What if I want to create real hardware in the cloud, and build a project like those in Circuit Cellar articles? This is where I see the innovation that is changing the future of how we make electronics. We now have cloud platforms that provide you with the experience of using actual parts from vendors and interfacing them with a microcontroller. Component lists including servo motors, IR remotes with buttons, LCDs, buzzers with sound, and accelerometers are needed if you’re actually building a project. Definitive parts carried by vendors and not just generic ICs are crucial. Ask any design engineer—they have their typical parts that they reuse and trust in every design. They need to verify that these parts move and work, so having an online platform with these parts allows for a real world simulation.

An Arduino IDE that allows for real-time debugging and stepping through code in the cloud is powerful. Advanced microcontroller IDEs do not have external components in their simulators or environment. A platform that can interconnect a controller with external components in simulation mirrors real life closer than anything else. By observing rises in computer processing power, many opportunities may be realized in the future with other more complex MCUs.

Most hardware designers are unaware of the newest cloud offerings or have not worked with a platform enough to evaluate it as a game-changer. But imagine if new electronics makers and existing engineers could learn and innovate without hardware for free in the cloud.

I remember spending considerable time working on circuit boards to learn the hardware “maker” side of electronics. I would typically start with a breadboard to build basic circuits. Afterwards it was migrated to a protoboard to build a smaller, robust circuit that could be soldered together. Several confident projects later, I jumped to designing and producing PCB boards that eventually led to an entirely different level in the semiconductor industry. Once the boards were designed, all the motors, sensors, and external parts could be assembled to the board for testing.

Traditionally, an assembled PCB was needed to run the hardware design—to test it for reliability, to program it, and to verify it works as desired. Parts could be implemented separately, but in the end, a final assembled design was required for software testing, peripheral integration, and quality testing. Imagine how this is now different using a hardware simulation. The quality aspect will always be tied to actual hardware testing, but the design phase is definitely undergoing disruption. A user can simply modify and test until the design works to their liking, and then design it straight away to a PCB after several online designs failures, all without consequence.

With an online simulation platform, aspiring engineers can now have experiences different from my traditional one. They don’t need labs or breadboards to blink LEDs. The cloud equalizes access to technology regardless of background. Hardware designs can flow like software. Instead of sending electronics kits to countries with importation issues, hardware designs can be shared online and people can toggle buttons and user test it. Students do not have to buy expensive hardware, batteries, or anything more than a computer.

An online simulation platform also affects the design cycle. Hardware design cycles can be fast when needed, but it’s not like software. But by merging the two sides means thousands can access a design and provide feedback overnight, just like a Facebook update. Changes to a design can be done instantly and deployed at the same time—an unheard of cycle time. That’s software’s contribution to the traditional hardware one.
There are other possibilities for hardware simulation on the end product side of the market. For instance, crowdfunding websites have become popular destinations for funding projects. But should we trust a simple video representing a working prototype and then buy the hardware ahead of a production? Why can’t we play with the real hardware online? By using an online simulation of actual hardware, even less can be invested in terms of hardware costs, and in the virtual environment, potential customers can experience the end product built on a real electronic design.

Subtle changes tend to build up and then avalanche to make dramatic changes in how industries operate. Seeing the early signs—realizing something should be simpler—allows you to ask questions and determine where market gaps exist. Hardware simulation in the cloud will change the future of electronics design, and it will provide a great platform for showcasing your designs and teaching others about the industry.

John Young is the Product Marketing Manager for Autodesk’s 123D Circuits (https://123d.circuits.io/) focusing on building a free online simulator for electronics. He has a semiconductor background in designing products—from R&D to market launch for Freescale and Renesas. His passion is finding the right market segment and building new/revamped products. He holds a BSEE from Florida Atlantic University, an MBA from the Thunderbird School of Global Management and is pursuing a project management certification from Stanford.

Industrial Drive Control SoC to Support Digital and Analog Position Sensors

Texas Instruments’s new TMS320F28379D and TMS320F28379S microcontrollers are an expansion to the C2000 Delfino microcontroller portfolio. When combined with DesignDRIVE Position Manager technology, they enable simple interfacing to position sensors. Based on the real-time control architecture of C2000 microcontrollers, the DesignDRIVE platform is ideal for the development of industrial inverter and servo drives used in robotics, elevators, and other industrial manufacturing applications.TI - TMS320F

With the C2000 DesignDRIVE development kit, you investigate a variety of motor drive topologies. DesignDRIVE is supported by the C2000 controlSUITE package and includes specific examples of vector control of motors, incorporating current, speed, and position loops, to help developers jumpstart their evaluation and development. In addition, users can download Texas Instruments’s Code Composer Studio integrated development environment (IDE), providing code generation and debugging capabilities. You can download reference interface and power supply designs for motor drives.

The TMS320F28379D and TMS320F28379S microcontrollers are now sampling starting at $17.20. The DesignDRIVE Kit (TMDXIDDK379D) costs $999.

Source: Texas Instruments

Boost Arduino Mega Capability with 512-KB SRAM & True Parallel Bus Expansion

The Arduino MEGA-2560 is a versatile microcontroller board, but it has only 8 KB SRAM. SCIDYNE recently developed the XMEM+ to enhance a standard MEGA in two ways. It increases SRAM up to 512 KB and provides True Parallel Bus Expansion. The XMEM+ plugs on top using the standard Arduino R3 stack-through connector pattern. This enables you to build systems around multiple Arduino shields. Once enabled in software, the XMEM+ becomes an integral part of the accessible MEGA memory.Scidyne

The XMEM+ also provides a fixed 23K Expansion Bus for connecting custom parallel type circuitry. Buffered Read, Write, Enable, Reset, 8-bit Data, and 16-bit Address signals are fully accessible for off-board prototyping. The XMEM+ makes any Arduino MEGA system much better suited for memory-intensive applications involving extended data logging, deep memory buffers, large arrays, and complex data structures. Target applications include industrial control systems, signage, robotics, IoT, product development, and education.

The introductory price is $39.99.

Source: SCIDYNE Corp.

Dual-Core, Runtime-Reconfigurable Processor for Low-Power Applications

Imsys has developed a dual-core, runtime-reconfigurable processor that can run at 350 MHz with an active power consumption of 19.7 µW/MHz using one core. Intended for low-power applications, 97% of the processor’s transistors are used in memory blocks. The cores share memories and a five-port grid network router (NoC). Memory management is handled by microcode, and memory is closely integrated with the processor without the need for an ordinary cache controller. The active consumption of each core—executing from RAM, including its consumption there—is 6.9 mW at 350 MHz.

Imsys’s processor is suitable for sensor nodes powered by energy harvesting in the Internet of Things (IoT), as well as in many-core chips for microservers and robotics. Microcode, as opposed to logic gates, is compact and energy efficient. Imsys uses extensive microprogramming to accomplish a rich set of instructions, thereby reducing the number of cycles needed without energy inefficient speculative activity and duplicated hardware logic. Each core has two instruction sets, one of which executes Java and Python directly from the dense JVM bytecode representation. C code is compiled to the other set with unparalleled density. Internal microcode is used for computationally intensive standard routines, such as crypto algorithms, which would otherwise be assembly coded library routines or even special hardware blocks. Optimizing CPU intensive tasks by microcode can reduce execution time and energy consumption of by more than an order of magnitude compared to C code.

The rich instruction set optimized for the compiler reduces the memory needed for software. And just like the microcoded algorithms, it reduces the number of clock cycles needed for execution. This platform has a certified JVM and uses an RTOS kernel certified to ISO 26262 safety standard for automotive applications. The development tools will be enhanced with the support enabled by the LLVM infrastructure. A new instruction set optimized for an LLVM backend has been developed and is being implemented in the coming hardware generation.

Source: Imsys

Low-Power Apollo Microcontroller Now in Volume Production

Ambiq Micro’s Apollo MCU—which was demonstrated to consume less than half the energy of other microcontrollers in real-world applications (EEMBC ULPBench benchmark)—is now available for shipping for high-volume consumer applications. The microcontroller features active mode current around 34 µA/MHz when running from flash memory and sleep mode current less than 150 nA. Built around an ARM M4 core with a floating-point unit, it’s available with 64 to 512 KB of embedded flash memory. In addition, it includes a 10-bit ADC and a variety of serial interfaces.  AMB012 Ambiq Available in both BGA and WLCSP packages, the Apollo MCU is available for immediate delivery with prices starting at $1.50 in 10,000-unit quantities.

Source: Ambiq Micro

An Introduction to Verilog

If you are new to programming FPGAs and CPLDs or looking for a new design language, Kareem Matariyeh has the solution for you. In this article, he introduces you to Verilog. Although the hardware description language has been used in the ASIC industry for years, it has all the tools to help you implement complex designs, such as a creating a VGA interface or writing to an Ethernet controller. Matariyeh writes:

Programmable logic has been around for well over two decades. Today, due to larger and cheaper devices on the market, FPGAs and CPLDs are finding their way into a wide array of projects, and there is a plethora of languages to choose from. VHDL is the popular choice outside of the U.S. It is preferred if you need a strong typed language. However, the focus of this article will be on another popular language called Verilog, which is a hardware description language that is similar to the C language.

Typically, Verilog is used in the ASIC design industry. Companies such as Sun Microsystems, Advanced Micro Devices, and NVIDIA use Verilog to verify and test new processor architectures before committing to physical silicon and post-fab verification. However, Verilog can be used in other ways, including implementing complex designs such as a VGA interface. Another complex design such as an Ethernet controller can also be written in Verilog and implemented in a programmable device.

This article is mostly tailored to engineers who need to learn Verilog and do not know or know little about the language. Those who know VHDL will benefit from reading this article as well and should be able to pick up Verilog fairly quickly after reviewing the example listings and referring to the Resources at the end of the article. This article does not go over hardware, but I have included some links that will help you learn more about how the hardware interacts with this language at the end.

THE VERILOG LANGUAGE

First, it is best to know what variable types are available in Verilog. The basic types available are: binary, integer, and real. Other types are available but they are not used as often as these three. Keep everything in the binary number system as much as possible because type casting can cause post-implementation issues, but not all writers are the same. Binary and integer types have the ability to use other values such as “z” (high impedance) and “x” (don’t care). Both are nice to have around when you want a shared bus between designs or a bus to the outside world. Binary types can be assigned by giving an integer value. However, there are times when you want to assign or look at a specific bit. Some of the listings use this notation. In case you are curious, it looks like this: X’wY, where X is the word size, w is the number base—b for binary, h for hex—and Y is the value. Any value without this is considered an integer by default. Keeping everything in binary, however, can become a pain in the neck especially when dealing with numbers larger than 8 bits.Table1

Table 1 shows some of the variable types that are available in Verilog. Integer is probably the most useful one to have around because it’s 32 bits long and helps you keep track of numbers easily. Note that integer is a signed type but can also be set with all “z” or “x.” Real is not used that much, when it is used the number is truncated to an integer. It is best to keep this in mind when using the real type, granted it is the least popular compared to binary and integer. When any design is initialized in a simulator, the initial values of a binary and integer are all “x.” Real, on the other hand, is 0.0 because it cannot use “x.” There are other types that are used when interconnecting within and outside of a design. They are included in the table, but won’t be introduced until later.Table2

Some, but not all, operators from C are in Verilog. Some of the operators available in Verilog are in Table 2. It isn’t a complete list, but it contains most of the more commonly used operators. Like C, Verilog can understand operations and perform implicit casting (i.e., adding an integer with a 4-bit word and storing it into a binary register or even a real); typically this is frowned on mostly due to the fact that implicit casting in Verilog can open a new can of worms and cause issues when running the code in hardware. As long as casting does not give any erroneous results during an operation, there should be no show-stoppers in a design. Signed operation happens only if integers and real types are used in arithmetic (add, subtract, multiply) operations.

VERILOG MODULES

In Verilog, designs are called modules. A module defines its ports and contains the implementation code. If you think of the design as a black box, Verilog code typically looks like a black box with the top missing. Languages like Verilog and VHDL encourage black box usage because it can make code more readable, make debugging easier, and encourage code reuse. In Verilog, multiple code implementations cannot have the same module name. This is in stark contrast to VHDL, where architectures can share the same entity name. The only way to get around this in Verilog is to copy a module and rename it.

In Listing 1, a fairly standard shift register inserts a binary value at the end of a byte every clock cycle. If you’re experienced with VHDL, you can see that there aren’t any library declarations. This is mainly due to the fact that Verilog originated from an interpretive foundation. However, there are include directives that can be used to add external modules and features. Obviously, the first lines after the module statement are defining the modules’ port directions and type with the reserved words input and output. There is another declaration called inout, which is bidirectional but not in the listing. A module’s input and output ports can use integer and real, but binary is recommended if it is a top-level module.Listing1

The reg statement essentially acts like a storage unit. Because it has the same name as the output port it acts like one item. Using reg this way is helpful because its storage ability allows the output to remain constant while system inputs change between clock cycles. There is another kind of statement called wire. It is used to tie more than one module together or drive combinational designs. It will appear in later listings.

The next line of code is the always statement or block. You want to have a begin and end statement for it. If you know VHDL, this is the same as the process statement and works in the same fashion. If you are completely new to programmable logic in general, it works like this: “For every action X that happens on signals indicated in the sensitivity list, follow these instructions.” In some modules, there is usually a begin and an end statement. This is the equivalent of curly braces seen in C/C++. It’s best to use these with decision structures (i.e., always, if, and case) as much as possible.

Finally, the last statement is a logical left shift operation. Verilog bitwise operators in some instances need the keyword assign for the operation to happen. The compiler will tell you if an assign statement is missing. From there, the code does its insertion operation and then waits for the next positive edge of the clock. This was a pretty straightforward example; unfortunately, it doesn’t do much. The best way to get around that is to add more features using functions, tying-in more modules, or using parameters to increase flexibility.

TASKS & FUNCTIONS

Tasks and functions make module implementation clearer. Both are best used when redundant code or complex actions need to be split up from the main source. There are some differences between tasks and functions.

A task can call other tasks and functions, while a function can call only other functions. A task does not return a value; it modifies a variable that is passed to it as an output. Passing items to a task is also optional. Functions, on the other hand, must return one and only one value and must have at least one value passed to them to be valid. Tasks are well-suited for test benches because they can hold delay and control statements. Functions, however, have to be able to run within one time unit to work. This means functions should not be used for test benches or simulations that require delays or use sequential designs. Experimenting is a good thing because these constructs are helpful.

There is one cardinal rule to follow when using a function or task. They have to be defined within the module, unlike VHDL where functions are defined in a package to get maximum flexibility. Tasks and functions can be defined in a separate file and then attached to a module with an include statement. This enables you to reuse code in a project or across multiple projects. Both tasks and functions can use types other than binary for their input and output ports, giving you even more flexibility.Listing2

Listing 2 contains a function that essentially acts like a basic ALU. Depending on what is passed to the function, the function will process the information and return the calculated integer value. Tasks work in the same way, but the structure is a little different when dealing with inputs and outputs. As I said before, one of the major differences between a task and a function is that the former can have multiple outputs, rather than just one. This gives you the ability to make a task more complicated internally, if need be.Listing3

Listing 3 is an example of a task in action with more than one output. Note how it is implemented the same way as a function. It has to be defined and called within the module in order to work. But rather than define the task explicitly within the module, the task is defined in a separate file and an include directive is added in the module code just to show how functions and tasks can be defined outside of a module and available for other modules to use.

BUILDING WITH MODULES

If too much is added to a module, it can become so large that debugging and editing become a chore. Doing this also minimizes code reuse to the point where new counters and state machines are being recreated when just using small modules/functions from a previous project is more than adequate. A good way to get around these issues is by making multiple modules in the same file or across multiple files and creating an instantiation of that module within an upper-level module to use its abilities. Multiple modules are good to have for a pipelined system. This enables you to use the same kind of module over multiple areas of a system. Older modules can also be used this way so less time is used on constant recreation.Listing4

That is the idea of code reuse in a nutshell. Now I will discuss an example of code reuse and multiple modules. The shift register from Listing 1 is having its data go into an even parity generator and the result from both modules is output through the top-level module in Listing 4. All of this is done across multiple files in one listing for easier reading. In all modular designs, there is always a module called a top-level entity, where all of the inputs and outputs of a system connect to the physical world. It is also where lower-level entities are spawned. Subordinates can spawn entities below themselves as well (see Figure 1).Figure 1

Think of it as a large black box with smaller black boxes connected with wires and those small black boxes have either stuff or even smaller black boxes. Pretty neat, but it can get annoying. Imagine a situation where a memory controller for 10-bit addressing is created and then the address length needs to be extended to 16 bits. That can be a lot of files to go through to change 10 to 16. However, with parameters all that needs to be changed is one value in one file and it’s all done.

PARAMETERS

Parameters are great to have around in Verilog and can make code reuse even more attractive. Parameters allow words to take the place of a numerical value like #define in C, but with some extra features such as overriding. Parameters can be put in length descriptors, making it easy to change the size of an output, input, or variable. For example, if a VGA generator had a color depth of 8 bits but needed to be changed to 32-bit color depth, then instead of changing the locations where the value occurs, only the value of the parameter would be changed and when the module was recompiled it would be able to display 32-bit color. The same can be done for memory controllers and other modules that have ports, wires, or registers with 1 bit or more in size. Parameters can also be overridden. This is performed just before or when a module is instantiated. This is helpful if the module needs to be the same all the time across separate projects that are using the same source, but needs to be a little different for another project. Parameters can also be used in functions and tasks as long as the parameter is in the same file the implementation code is in. Parameters with functions and tasks give Verilog the flexibility of a VHDL package, granted it really isn’t a package, because the implementation is located in a module and not in a separate construct.Listing5

There are many ways to override parameters. One way is by using the defparam keyword, which explicitly changes the value of the parameter in the instantiated module before it is invoked. Another way is by overriding the parameter when the module is being invoked. Listing 5 shows how both are done with dummy modules that already have defined parameters. The defparam method is from an older version of the language, so depending on the version of Verilog being used, make sure to pick the right method.

Download the entire article.

Rad Tolerant 3.3-V CAN Transceivers for Satellite Communications

Intersil Corp. recently announced  the industry’s first radiation-tolerant, 3.3-V controller area network (CAN) transceivers that are fully QML-V qualified and compliant with the ISO11898-2 physical layer standard. The three new ISL7202xSEH CAN transceivers provide reliable serial data transmission between a CAN controller and CAN bus at speeds up to 1 Mbps. Up to 120 of Intersil’s ISL7202xSEH transceivers can be connected to a single CAN bus to reduce cabling/harness size, weight and power (SWAP) costs. This weight and mass reduction of up to 18% allows system engineers to add millions of dollars in satellite functionality, and eliminate the extra cabling and tradeoffs associated with current point-to-point interface solutions.isl7202 Intersil

The ISL72026SEH, ISL72027SEH, and ISL72028SEH 3.3-V CAN transceivers deliver ultra-high performance in the most demanding environments by leveraging Intersil’s proprietary silicon on insulator process, which provides single event latch-up (SEL) and single event burn-out (SEB) robustness in heavy ion environments. With the emergence of all-electric propulsion satellites that maximize payload but take longer to reach final orbit, customers require higher total dose testing for mission assurance. Intersil’s CAN transceivers are low dose rate tested up to 75 krad on a wafer-by-wafer basis, and apply single event transient (SET) mitigation techniques to reduce system level bit error rates, providing predictable performance. They are also “cold spare” redundant capable, allowing the connection of additional unpowered transceivers to the CAN bus. This mission-critical capability maximizes system life.

  • The ISL7202xSEH family offers a number of unique features:
  • The ISL72026SEH includes a loopback test capability that allows node diagnostics and reporting while the system is transmitting data

It offers split termination output using the VREF pin to provide a VCC/2 output reference. This improves network electromagnetic compatibility and stabilizes the bus voltage, preventing it from drifting to a high common-mode voltage during inactive periods. The ISL72028SEH includes a low power shutdown mode that switches off the driver and receiver to draw 50 µA for power conservation.

Key features and specs:

  • Electrically screened to SMD 5962-15228, and compatible with ISO11898-2
  • Delivers 4-kV human body model (HBM) ESD protection on all pins
  • 3- to 3.6-V supply range, –7 to 12 V common-mode input voltage range, 5-V tolerant logic inputs, and bus pin fault protection to ±20-V terrestrial and ±18 V in orbit
  • Cold spare powered down devices do not affect active devices operating in parallel
  • Three selectable driver rise and fall times
  • Glitch free bus I/O during power-up and power-down
  • Full fail-safe receiver: open, short, terminated/undriven
  • Hi Z input allows for 120 nodes on the bus and data rates up to 1 Mbps
  • Low quiescent supply current of 7 mA
  • Thermal shutdown
  • Low dose rate (0.01 rad(Si)/s) radiation tolerance of 75 krad(Si)
  • SEL/B immune up to LET 60 MeV.cm2/mg

The ISL72026SEH, ISL72027SEH and ISL72028SEH 3.3V CAN transceivers are available in eight-lead ceramic flatpack packages.

Source: Intersil Corp.

STMicro’s New Advanced 32-Bit Secure Microcontroller

STMicroelectronics has introduced the first member of the third generation of its ST33 series of secure microcontrollers based on the 32-bit ARM SecurCore SC300 processor. The ST33J2M0, which provides 2-MB flash program memory, is intended for secure applications including embedded Secure Element (eSE), Single Wire Protocol (SWP) SIMs for NFC applications, and embedded Universal Integrated Circuit Card (UICC). The secure microcontroller includes the highest performance and integrated crypto-accelerators that together with the industry’s fastest clock speed in a secure microcontroller enable the highest performance for fast application execution. It also features a new hardware architecture with strong and multiple fault-protection mechanisms covering the CPU, memories, and buses to facilitate the development of highly secure software.s.

The ST33J2M0 features multiple hardware accelerators for advanced cryptographic functions. The EDES peripheral provides a secure Data Encryption Standard (DES) algorithm implementation, while the NESCRYPT crypto-processor efficiently supports the public key algorithm. The AES peripheral ensures secure and fast AES algorithm implementation.

ST33J2M0 samples are available as wafers or housed in VQFN and WLCSP packages.

Connected Home Solutions with ZigBee and Thread-Ready Connectivity

Silicon Labs recently introduced a series of comprehensive reference designs that reduce time to market and simplify the development of ZigBee-based home automation, connected lighting and smart gateway products. The first in a series of Internet of Things (IoT) solutions, the new reference designs include hardware, firmware, and software tools for developing high-quality connected home solutions based on Silicon Labs’s ZigBee “Golden Unit” Home Automation (HA 1.2) software stack and ZigBee SoC mesh networking technology.SiliconLabs IoT-SolutionsSilicon Labs’ ZigBee connected lighting reference designs feature wireless lighting boards and a plug-in demo board. The Golden Unit ZigBee stack allows LED lights to reliably join, interoperate, and leave a mesh network. The connected lights can support white, color temperature tuning, and RGB color settings as well as dimming.

Silicon Labs’ ZigBee-based home automation reference designs include a capacitive-sense dimmable light switch and a small door/window contact sensor. The light switch provides color, color tuning, and dimming control capabilities. As opposed to conventional switches, the wireless, battery-powered switches have no moving parts and are easy to place anywhere in a home. The switch design includes Silicon Labs’s EFM8 capacitive sensing microcontroller to detect different user gestures (touch, hold, and swipe). The contact sensor reference design provides all the tools needed to create wireless, battery-powered sensors used to monitor door and window positions (open or closed).

Silicon Labs offers two ZigBee gateway options to complement the reference designs:

  • A plug-and-play USB virtual gateway that works with any PC development platform and supports the Windows, OS X, and Linux environments as a virtual machine
  • An out-of-the-box Wi-Fi/Ethernet gateway reference design based on an embedded Linux computer system

Both gateway options enable you to control and monitor ZigBee HA 1.2-compliant end nodes through Wi-Fi with any device with a web browser, such as a smartphone or tablet. With an intuitive, web-based user interface, you can easily create rules between ZigBee end devices including lights, dimmable light switches, and contact sensors.

Silicon Labs’ connected lighting, home automation, and smart gateway reference designs are currently available. The RD-0020-0601 and RD-0035-0601 connected lighting reference designs cost $49. The RD-0030-0201 contact sensor reference design is $39. The RD-0039-0201 capacitive-sense dimmable light switch reference design is $29. The USB virtual gateway is $49. The out-of-the-box Wi-Fi/Ethernet gateway reference design is $149.

Source: Silicon Labs 

New Software for Creating Simulation Apps

COMSOL recently released COMSOL Multiphysics 5.2 with the latest version of the Application Builder and COMSOL Server products. The new software enables organizations to share simulation work, from design and development to production and testing. This version of COMSOL Multiphysics and COMSOL Server simulation software environment provides new features, improved stability, and faster execution. Notable upgrades to the Application Builder available in COMSOL Multiphysics include the new Editor Tools for easy creation of user interface components, commands for dynamic updates of graphics, and more control over the deployment of simulation apps. Numerous updates, new features, and simulation application examples are also available for the add-on electrical, mechanical, fluid, and chemical products.COMSOL_5.2

The new software makes it possible to update graphics while running an app. The app designer can present app users with different plots while solving; this takes them through the progression of the solution process and presents them, for example, with geometry, mesh, and solution plots. The app designer can also customize the graphics toolbar with new buttons and include camera movements.

To demonstrate the power of the Application Builder, a wide variety of new apps have been added to the extensive Application Libraries showcasing the capabilities of the Application Builder. The Application Libraries include apps ranging from membrane dialysis, water treatment, thermoelectric cooling, heat exchangers, touchscreen design, magnetic prospecting, piezoacoustic transducers, muffler design, MEMS sensors, and pressure vessels.

Version 5.2 also introduces enhancements to the existing functionalities of COMSOL Multiphysics and its add-on products. Users will benefit from more flexible license management, Users of the Structural Mechanics Module and the AC/DC Module will benefit from the new External Materials functionality allowing materials to be algorithmically defined by shared library files written in the C language. The most prominent use of this new functionality will be for nonlinear materials that include hysteresis (history dependency) and irreversibility effects.

Source: COMSOL

Issue 304: EQ Answers

Problem 1—The following circuit was designed to be an inrush current limiter for the large (40,000 µF) capaitor C1. R7 represents the application load of about 180 mA at 9 V.eq0671_fig1

The load on the 9-V source (Vin) needed to be limited to about 350 mA, and the circuit performs remarkably well, as shown in the simulation. The current -Id(M1) is the drain current of the MOSFET.eq0671_fig2

However, note that the circuit does not sense the source or load current directly. How then does it work?

Answer 1—Basically, the circuit works by using the C2-R3 combination as a model (or analog) for the charging of C1. Instead of sensing the current in C1 directly, R3 senses the current in C2, and it is assumed that this value is proportional to the current in C1, which is true as long as the voltage across R3 is a small fraction of the total.

Whenever there is a drop across R3 because of current through C2, the drive to the pass transistor is reduced.

The Thevenin equivalent of the base drive to Q1 is 1.5 V and 120 kΩ, so if the voltage across R3 ever rises as high as 1.5 V – 0.6 V = 0.9 V, Q1 is cut off altogether, removing the drive from M1 as well. Assuming a VBE for Q1 of 0.65 , this would occur at a C2 current of about 0.85 V/10 kΩ = 85 µA, which would correspond to a current in C1 of 85 µA × (40000 µF / 12 µF) = 280 mA.

By adjusting the resistor and capacitor values, you can change that limiting current value. Note that the total current through M1 (and the power supply) is the C1 charging currrent plus the rising load current through R7, so pick the limit value accordingly.

This analogy works because the basic equation of a capacitor says that the current through a capacitor is proportional to the rate of change of the voltage across it, and also to its capacitance:

i(t) = C dV(t) / dt

The assumption is that the voltage across R3 is “small”, which means that V(t) is essentially the same for both capacitors. This means that the current through each is directly proportional to its capacitance.

In this specific case, the voltage across R3 can be as high as 0.85 V, which is aobut 10% of the supply voltage, so the proportionality isn’t as precise as it could be, but it’s good enough for this purpose.

Problem 2—The actual charging current seems to be limited to about 230 mA. Why is this?

Answer 2—Transistor Q1 also contributes to the current flowing through R3, which means that the current through C2 must be corresponding less, which means that the current through C1 must be less, too.

Working backward, if the current through C1 is 230 mA, then the current through C2 would be about 230 mA × (12 µF / 40,000 µF) = 69 µA.

That implies that Q1 is passing about 85 µA – 69 µA = 16 µA.

This current passing through R1 would create a voltage drop of about 16 µA × 220 kohm = 3.52 V, which represents the threshold voltage of M1.

Problem 3—What is the function of C3?

Answer 3—C3 provides a “soft start” function for the circuit. If the base of Q1 were to rise instantly to 1.5 V, then M1 would be turned on fairly hard, creating an initial load spike on the power source.

Note that Q1 can turn on M1, charging its gate capacitance through R2. However, M1 can only be turned off by dicharging that capacitacne through R1, making turn-off much slower than turn-on.

As noted before, these resistances need to be high so that the current that they contribute to R3 is small relative to the current through C2.

Problem 4—Are there any special considerations on the selection of M1?

Answer 4—As long as M1 can handle the voltage and the current, and that the maximum VGS it sees is controllede by appropriate selection of R1 and R2, there’s really nothing special required.

Pay attention to the SOA (safe operating area) diagram in the datasheet. Plot some sample voltage and current values from the simulation in order to make sure it stays in the safe area.

Also, be sure to give it an adequate way to dissipate the pulse of heat associated with the charging surge of C1 without having its temperature rise too high.

Electrical Engineering Crossword (Issue 305)

The answers to Circuit Cellar’s December 2015 electrical engineering crossword puzzle are now available.305-grid-(key)

Across

  1. RADIAN—Rad
  2. SIEMENS—1/ohm
  3. VECTOR—Has magnitude and direction
  4. REPEATER—Acquires and retransmits signals
  5. INTERFERENCE—Distortion
  6. PINS—GND, VCC, SCK, SDA
  7. HORSEPOWER—746 W
  8. DOUGHNUT—Torus
  9. SCALAR—No direction, but has magnitude

Down

  1. BERYLLIUMOXIDE—BeO
  2. MONOPHONIC—Mono
  3. USEREXPERIENCE—UX
  4. PRIME—23, 149, 337
  5. TESLA—Wardenclyffe Tower
  6. CONTACT—Part of a switch that opens and closes a circuit
  7. MICROVOLT—10 sup -6 V
  8. RMS—Quadratic mean
  9. GOOGOL—10 super 100
  10. QUINT—Five

Electrical Engineering Crossword (Issue 304)

The answers to Circuit Cellar’s November 2015 electrical engineering crossword puzzle are now available.304-empty-grid-(key)

Across

  1. DRYCELL—A battery cell with a paste electrolyte (two words)
  2. RAIL—Part of a power supply that has the highest voltage or current-delivery capability
  3. DECADE—10 consecutive units
  4. TELSA—Flex density unit
  5. LOGARITHM—Computational system based on powers of 10
  6. PEAK—Brief increase in signal energy
  7. SHUNT—To bypass
  8. SIBILANCE—Vocal sound
  9. INFRASONIC—Range of sound frequencies below 20 Hz

Down

  1. PASCAL—1 newton/cm2
  2. XTAL—Crystal
  3. REACTANCE—X
  4. GATE—Automatic control circuit that sets the threshold level at which a dynamic processor starts to take effect
  5. ZERO—Null
  6. DRIFT—Shift of circuit parameters away from optimum settings
  7. TANGENT—Straight line that touches a circle at a single point
  8. CORE—Hub around which the windings of a transformer or inductor are wrapped
  9. EMITTER—Region of a bipolar transistor into which electrons are introduced to the semiconductor material
  10. UNIPIVOT—Single pivot
  11. NANO—1,000,000,000

New Dual-Channel USB Port Power Controller

Microchip Technology recently expanded its programmable USB-port power controller portfolio with the dual-channel UCS2112. This UCS2112 port power controller supports two ports, with eight programmable continuous current limits for each port, ranging from 0.53 to 3 A for faster charging times at higher currents. You can use it as is or with USB hubs to create a complete charging or USB communication system.Microchip UCS2112

 

The UCS2112 port power controller is supported by Microchip’s new $140 UCS2112 Evaluation Board. The UCS2112 is available for sampling and volume production in a 20-pin QFN package. Pricing starts at $1.80 each, in 5,000-unit quantities. Microchip Eval Board USC21212

Source: Microchip Technology

Free, Commercial-Quality IDE for the ARM Development Community

Atollic recently launched the new TrueSTUDIO Lite, which is a free, commercial-quality IDE without code-size or microcontroller family limitations.  TrueSTUDIO Lite offers the ARM development community a high-quality tool to standardize on. Based on an open standard tools platform of Eclipse/GCC/GDB, that TrueSTUDIO Lite features commercial-quality modifications, start-up wizards, and target support for ARM-based microcontrollers. ATC020 AtollicTrueSTUDIO

Atollic is also introducing a low-cost upgrade path to TrueSTUDIO Pro, which includes static code analysis and advanced debugging capabilities such as event-, data-, and instruction-tracing, live variable watch, crash analysis, and RTOS-aware debugging. The Pro edition includes full technical support. You can add these capabilities with a low-cost, pay-as-you-go subscription option.

You can download TrueSTUDIO Lite for free. TrueSTUDIO Pro starts at $59 per month for a 12-month prepaid subscription license.

Source: Atollic